EP0211384A2
Expired / Lapsed
EP
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Prefetch monitor
Assignee: Wang Laboratories Inc
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Filing: 1986-07-30
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Granted: —
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Expires: 2006-07-30
Abstract
Abstract An information processing system includes a processor means responsive to instructions for performing operations. The processor means includes instruction queue means for fetching and storing instructions in advance of execution and the system is responsive to certain of the instructions for causing execution of a corresponding sequence of instructions. A prefetch monitor means (28) includes a means (34) for detecting instructions which may result in the execution of a corresponding sequence of instructions. The prefetch monitor means further includes an instruction substitution means (70, 72, 74, 76) which is responsive to the detecting means for inhibiting the reading of following instructions from the memory means to the processor means and is responsive to instruction fetching operation of the processor means for reading null instructions to the processor means. The prefetch monitor means (28) also includes a synchronization means (64, 66) which is responsive to fetching operation of the processor means for detecting transfer of execution to a next valid instruction, wherein the substitution means (70,72,74, 76) is responsive to the synchronization means for resuming reading of instructions from the memory means to the processor means with the next valid instruction. The synchronization means includes means for maintaining synchronization between the operations of substituting null instructions and the execution of the instructions.
Inventors
- 👤 David J. Angel
- 👤 Gary Alan Cardone
- 👤 Mark Denton Holbrook
- 👤 James Phillip Moskun
- 👤 Bruce Patterson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 18:40
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
126 words
1) In an information processing system (10) including memory means (12) for storing instructions, processor means (14) responsive to the instructions for performing operations, the processor means including instruction queue means for fetching and storing instructions in advance of execution, and means responsive to certain of the instructions for causing execution of a corresponding sequence of instructions, prefetch monitor means (28), comprising: means (34) for detecting the instructions which may result in the execution of a corresponding sequence of instructions, and instruction substitution means (70, 72, 74, 76) responsive to the detecting means for inhibiting the reading of following instructions from the memory means to the processor means, and responsive to instruction fetching operation of the processor means for reading null instructions to the processor means.
Claim 2
Dependent Claim
126 words
1) In an information processing system (10) including memory means (12) for storing instructions, processor means (14) responsive to the instructions for performing operations, the processor means including instruction queue means for fetching and storing instructions in advance of execution, and means responsive to certain of the instructions for causing execution of a corresponding sequence of instructions, prefetch monitor means (28), comprising: means (34) for detecting the instructions which may result in the execution of a corresponding sequence of instructions, and instruction substitution means (70, 72, 74, 76) responsive to the detecting means for inhibiting the reading of following instructions from the memory means to the processor means, and responsive to instruction fetching operation of the processor means for reading null instructions to the processor means.
Claim 3
Dependent Claim
62 words
2) The prefetch monitor means of claim 1, further comprising: synchronization means (64, 66) responsive to fetching operation of the processor means for detecting transfer of execution to a next valid instruction, the substitution means (70, 72, 74, 76) responsive to the synchronization means for resuming reading of instructions from the memory means to the processor means with the next valid instruction.
Claim 4
Dependent Claim
15 words
3) The prefetch monitor means of claim 1, wherein: the null instructions are jump-to-self instructions.
Claim 5
Dependent Claim
39 words
4) The prefetch monitor means of claim 1, wherein the instructions which may result in the execution of a corresponding sequence of instructions result in a non-maskable interrupt which directs the system to execute a corresponding sequence of instructions.
Claim 6
Dependent Claim
48 words
5) The prefetch monitor means of claim 3, wherein: the instructions which may result in the execution of a corresponding sequence of instructions are foreign to the system, and a corresponding non-maskable interrupt results in the execution of a routine which emulates the execution of the foreign instruction.
Claim 7
Dependent Claim
76 words
6) The prefetch monitor means of claim 2, wherein the synchronization means comprises: instruction pointer means (64) for receiving an initial fetch address representing a valid next instruction and, responsive to fetching operation of the processor means, generating successive instruction addresses, and comparison means (66) responsive to fetching addresses generated by the processor means and to successive instruction pointer addresses for indicating a fetching address which is out of sequence with a corresponding instruction pointer address.
Claim 8
Dependent Claim
84 words
7) The prefetch monitor means of claim 1, further comprising: means (40, 42, 60, 62) for detecting instructions which may result in an out of sequence transfer of execution, the substitution means being responsive to the detection of an instruction which may result in an out of sequence transfer of execution for inhibiting the reading of following instructions from the memory means to the processor means, and responsive to instruction fetching operation of the processor means for reading null instructions to the processor means.
Claim 9
Dependent Claim
28 words
8) The prefetch monitor means of claim 7, wherein the instructions which may result in an out of sequence transfer of execution include conditional and unconditional jump instructions.
Claim 10
Dependent Claim
63 words
9) The prefetch monitor means of claim 7, further comprising: synchronization means (64, 66) responsive to fetching operation of the processor means for detecting transfer of execution to a next valid instruction, the substitution means (70, 72, 74, 76) being responsive to the synchronization means for resuming reading of instructions from the memory means to the processor means with the next valid instruction.
Claim 11
Dependent Claim
125 words
10) The prefetch monitor means of claim 9, wherein the instructions which may result in an out of sequence transfer of execution include conditional jump instructions and the synchronization means further comprises: means (60) responsive to a conditional jump instruction for determining the distance of the conditional jump, means (62) responsive to fetching operation of the processor means for storing and successively decrementing the jump distance, and means (62, 78) responsive to the stored and decremented jump distance for indicating the fetching of an instruction to which execution has transferred, the substitution means (70, 72, 74, 76) being responsive to the synchronization means for resuming reading of instructions from the memory means to the processor means with the instruction to which execution has been transferred.
Claim 12
Dependent Claim
110 words
11) The prefetch monitor means of claim 2, wherein the synchronization means further comprises: means (34, 38, 44) responsive to the instructions for determining the number of bytes in an instruction, means (46, 48, 50, 54) responsive to fetching operation of the processor means for storing and successively decrementing the number of bytes in the instruction, and means (56, 58) responsive to the stored and decremented number of bytes for indicating the start of a next instruction, the substitution means (70, 72, 74, 76) being responsive to the synchronization means for resuming reading of instructions from the memory means to the processor means with the start of the next instruction.
References Cited (Backward Citations)
No citation records indexed.
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