Patent US5218686A successfully refreshed from Google Patents.
US5218686A
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Combined synchronous and asynchronous memory controller
Assignee: Hewlett Packard Development Co LP
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Filing: 1989-11-03
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Granted: 1993-06-08
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Expires: 2009-11-03
Abstract
Abstract A memory controller has an asynchronous portion and a synchronous portion. The synchronous portion is used when the system processor is accessing the memory, while the asynchronous portion is used when control of the memories is held by a DMA controller or a bus master located on a standardized bus.
Inventors
- 👤 John S. Thayer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:19
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
247 words
A computer system comprising: a microprocessor providing address, data and control signals according to a first convention, control signals according to said first convention including a signal indicating availability of address values, and a signal indicating completion of a cycle; bus control means providing address, data and control signals according to a second convention, control signals according to said second convention including a signal indicating an address portion of a cycle and a signal indicating a data portion of a cycle, wherein said first and second convention control signals are substantially dissimilar; a bus for conveying address, data and control signals; means for coupling said microprocessor signals to said bus at certain periods and for coupling said bus control means signals to said bus at other periods; memory means having address and control inputs and data lines; means for coupling said memory means address inputs and data lines to said bus; memory controller means coupled to said bus, said memory means control inputs, and said memory means coupling means for controlling said memory means to store and provide data at proper times of both said first and said second conventions, wherein said memory controller means includes a synchronous portion for use when said microprocessor is coupled to said bus and said control signals according to said first convention are utilized and an asynchronous portion for use when said bus control means is coupled to said bus and said control signals according to said second convention are utilized.
Claim 2
Dependent Claim
247 words
A computer system comprising: a microprocessor providing address, data and control signals according to a first convention, control signals according to said first convention including a signal indicating availability of address values, and a signal indicating completion of a cycle; bus control means providing address, data and control signals according to a second convention, control signals according to said second convention including a signal indicating an address portion of a cycle and a signal indicating a data portion of a cycle, wherein said first and second convention control signals are substantially dissimilar; a bus for conveying address, data and control signals; means for coupling said microprocessor signals to said bus at certain periods and for coupling said bus control means signals to said bus at other periods; memory means having address and control inputs and data lines; means for coupling said memory means address inputs and data lines to said bus; memory controller means coupled to said bus, said memory means control inputs, and said memory means coupling means for controlling said memory means to store and provide data at proper times of both said first and said second conventions, wherein said memory controller means includes a synchronous portion for use when said microprocessor is coupled to said bus and said control signals according to said first convention are utilized and an asynchronous portion for use when said bus control means is coupled to said bus and said control signals according to said second convention are utilized.
Claim 3
Dependent Claim
37 words
The computer system of claim 1, wherein said microprocessor and said memory controller means each have a clock signal input, the computer system further comprising: a clock signal coupled to said microprocessor and said memory controller means.
Claim 4
Dependent Claim
27 words
The computer system of claim 2, wherein said memory controller means synchronous portion includes a state machine and said state machine is advanced by said clock signal.
Claim 5
Dependent Claim
42 words
The computer system of claim 3, wherein said memory means coupling means includes a buffer having an output enable input and a plurality of latches having output enable inputs and wherein said memory controller means provides signals to said output enable inputs.
Claim 6
Dependent Claim
27 words
The computer system of claim 4, wherein said memory controller means synchronous portion provides a plurality of said output enable signal based on said state machine state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |