EP0135879A2
Expired / Lapsed
EP
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Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system
Assignee: International Business Machines Corp
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Filing: 1984-09-10
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Granted: —
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Expires: 2004-09-10
Abstract
Abstract © An interface circuit for connecting a memory controller (208) to either a synchronous bus or an asynchronous bus. The interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus and synchronizing means (198) for synchronizing memory access request signals with a local clock when the interface circuit is coupled to an asynchronous bus. An interface method of connecting memory circuits to either a synchronous bus or an asynchronous bus. The method comprises the generation of a mode signal indicative of the type of bus, and the synchronization of the memory access request signals with a local clock when the mode signals indicate an asynchronous bus.
Inventors
- 👤 David Ernest Finlay
- 👤 Kent Steven Norgren
- 👤 Frankie Sherwood Shook
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:50
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
219 words
Interface circuit for connecting a memory controller (208) with a synchronous bus or an asynchronous bus to supply a memory access request signal from the bus system to the memory controller, the memory controller (208) carrying out internal memory operations in accordance with said memory access request signal and generating a response signal when those operations are complete, and the interface circuit being connected for receiving said response signal and for supplying said signal to the bus, characterized in that the interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus system to which the interface circuit is connected for passing a synchronous mode signal if synchronous type is indicated and for passing an asynchronous mode signal if asynchronous type is indicated, receiving circuits (199) for receiving said memory access request signal from the bus and for passing said signal to the memory controller (208), synchronizing circuits (198) connected to the receiving circuits (199) for synchronizing said memory access request signal with the timing of the memory controller (208) and logic circuits (206) connected between the synchronizing circuits (198) and the memory controller (208) and also connected to the switch means (197) for receiving the synchronous and asynchronous mode signals and for passing said memory access request signal to the memory controller (208).
Claim 2
Dependent Claim
219 words
Interface circuit for connecting a memory controller (208) with a synchronous bus or an asynchronous bus to supply a memory access request signal from the bus system to the memory controller, the memory controller (208) carrying out internal memory operations in accordance with said memory access request signal and generating a response signal when those operations are complete, and the interface circuit being connected for receiving said response signal and for supplying said signal to the bus, characterized in that the interface circuit comprises switch means (197) for supplying a signal indicative of the type of bus system to which the interface circuit is connected for passing a synchronous mode signal if synchronous type is indicated and for passing an asynchronous mode signal if asynchronous type is indicated, receiving circuits (199) for receiving said memory access request signal from the bus and for passing said signal to the memory controller (208), synchronizing circuits (198) connected to the receiving circuits (199) for synchronizing said memory access request signal with the timing of the memory controller (208) and logic circuits (206) connected between the synchronizing circuits (198) and the memory controller (208) and also connected to the switch means (197) for receiving the synchronous and asynchronous mode signals and for passing said memory access request signal to the memory controller (208).
Claim 3
Dependent Claim
45 words
Interface circuit according to claim 1, wherein the logic circuits (206) are also connected directly between the receiving circuits (199) and the memory controller (208) for passing said memory access request signal directly to the memory controller (208) when said synchronous mode signal is present.
Claim 4
Dependent Claim
58 words
Interface circuit according to claim 1 further including second logic circuits (206A) for generating a transfer acknowledge signal, and second receiving circuits for receiving a response signal from the memory controller (208) upon completion of memory internal operation and for passing said response signal to the second logic circuits (206A) for the generation of said transfer acknowledge signal.
Claim 5
Dependent Claim
108 words
Interface circuit according to claim 3, wherein the second logic circuits (206A) are connected to receive said synchronous and asynchronous mode signals and where said second receiving means is comprised of: first response circuits (210) for receiving said response signal from the memory controller (208) and passing said response signal to the second logic circuits (206A) for generating said transfer acknowledge signal when said synchronous mode signal is present, and second response circuits (213) for receiving said response signal from the memory controller (208) and passing said response signal to the second logic circuits (206A) for generating said transfer acknowledge signal when said asynchronous mode signal is present.
Claim 6
Dependent Claim
166 words
Interface method of connecting a memory controller (208) to either a synchronous bus or an asynchronous bus through a common interface circuit for receiving memory access request signals and responding with an acknowledge signal, comprising: setting said interface circuit to generate a synchronous mode signal if the memory controller (208) is connected to a synchronous bus and to generate an asynchronous mode signal if the memory controller (208) is connected to an asynchronous bus, receiving said memory access request signal in a receiving circuit (199) common to either synchronous or asynchronous connection, and passing said memory access request signal to logic circuits (206) and then to the memory controller (208) for performance of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said passing step including a synchronizing step if in asynchronous mode to synchronize said memory access request signal to a local memory clock signal, and not including said synchronizing step if in synchronous mode.
Claim 7
Dependent Claim
166 words
Interface method of connecting a memory controller (208) to either a synchronous bus or an asynchronous bus through a common interface circuit for receiving memory access request signals and responding with an acknowledge signal, comprising: setting said interface circuit to generate a synchronous mode signal if the memory controller (208) is connected to a synchronous bus and to generate an asynchronous mode signal if the memory controller (208) is connected to an asynchronous bus, receiving said memory access request signal in a receiving circuit (199) common to either synchronous or asynchronous connection, and passing said memory access request signal to logic circuits (206) and then to the memory controller (208) for performance of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said passing step including a synchronizing step if in asynchronous mode to synchronize said memory access request signal to a local memory clock signal, and not including said synchronizing step if in synchronous mode.
Claim 8
Dependent Claim
119 words
Interface method according to claim 5, wherein said interface circuit also provides common circuit elements for generating an acknowledgement signal to said memory access request signal upon completion of internal memory operation in accordance with said memory access request signal and in accordance with a read/write command signal, said method further including the steps of receiving a first response signal from the memory controller (208), passing said first response signal to second logic circuits (206A) for generating said acknowledgement signal when connected to a synchronous bus, receiving a second response signal from the memory controller (208), and passing said second response signal to the second logic circuits (206A) for generating said acknowledgement signal when connected to an asynchronous bus.
References Cited (Backward Citations)
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