Patent US1827613A successfully refreshed from Google Patents.
Patent US5218228A successfully refreshed from Google Patents.
US5218228A
Expired / Lapsed
US
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High voltage MOS transistors with reduced parasitic current gain
Assignee: Vishay Siliconix Inc
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Filing: 1992-03-11
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Granted: 1993-06-08
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Expires: 2012-03-11
Abstract
Abstract A method is disclosed which produces a high voltage MOS transistor with a deep retrograde N-well region, which includes a buried layer, said deep retrograde well region acting to increase the breakdown voltage of the MOS transistor and reduce the current gain of the inherent parasitic bipolar transistor. To achieve a high degree of control over the impurity concentration of the buried layer without affecting the impurity concentration in the N-well region, two dopants species are diffused or implanted in the N+ buried layer: one, a slow diffusing dopant, such as antimony or arsenic, and the other, a more rapidly diffusing dopant, such as phosphorus. A P- type epitaxial layer is grown over the buried layer and an N-well is formed in the epitaxial layer over the buried layer. Using this method, the high concentration of slow diffusing N type antimony or arsenic dopant in the buried layer will not out-diffuse into the N-well region and adversely affect the breakdown voltage between the source or drain and the N-well. The out-diffusing of the phosphorus into the epitaxial layer, however, will merge with the phosphorus diffusion from the top to form a uniform N type concentration in the N-well.
Inventors
- 👤 Richard K. Williams
- 👤 Robert W. Busse
- 👤 Richard A. Blanchard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10D30/603; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D30/01; H10D30/021; H10D30/0221; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10W; H10W15/00; H10W15/01
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
306 words
An MOS device comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; a source region of said first conductivity type formed in said upper well region; a drain region of said first conductivity type formed in said upper well region; a gate oxide layer formed over said upper well region between said source region and said drain region; and a control gate formed over said gate oxide layer.
Claim 2
Dependent Claim
306 words
An MOS device comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; a source region of said first conductivity type formed in said upper well region; a drain region of said first conductivity type formed in said upper well region; a gate oxide layer formed over said upper well region between said source region and said drain region; and a control gate formed over said gate oxide layer.
Claim 3
Dependent Claim
50 words
The MOS transistor of claim 1 further characterized in that said buried layer includes both said first dopant of said slow diffusing type and said second dopant of said fast diffusing type, and said upper and lower well regions substantially include only said second dopant of said fast diffusing type.
Claim 4
Dependent Claim
35 words
The MOS transistor of claim 1 wherein said drain region comprises a lightly doped drain extension of said first conductivity type contiguous with a more heavily doped drain region portion of said first conductivity type.
Claim 5
Dependent Claim
32 words
The MOS transistor of claim 1 further comprising an upper well contact region of said second conductivity type formed in said upper well region in said top surface of said epitaxial layer.
Claim 6
Dependent Claim
34 words
The MOS transistor of claim 1 wherein a size and an impurity concentration of said upper well region is such that a breakdown voltage of said MOS transistor is greater than approximately 130 volts.
Claim 7
Dependent Claim
299 words
A bipolar transistor device comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; a base region of said first conductivity type formed in said upper well region; an emitter region of said second conductivity type formed in said base region; and a collector region of said second conductivity type formed in said upper well region and not within said base region.
Claim 8
Dependent Claim
299 words
A bipolar transistor device comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; a base region of said first conductivity type formed in said upper well region; an emitter region of said second conductivity type formed in said base region; and a collector region of said second conductivity type formed in said upper well region and not within said base region.
Claim 9
Dependent Claim
50 words
The bipolar transistor of claim 6 further characterize and that said buried layer includes both said first dopant of said slow diffusing type and said second dopant of said fast diffusing type, and said upper and lower well regions substantially include only said second dopant of said fast diffusing type.
Claim 10
Dependent Claim
21 words
The bipolar transistor of claim 6 wherein said collector region extends down into said epitaxial layer to contact said buried layer.
Claim 11
Dependent Claim
34 words
The bipolar transistor of claim 6 wherein a size and an impurity concentration of said upper well region is such that a breakdown voltage of said bipolar transistor is greater than approximately 130 volts.
Claim 12
Dependent Claim
258 words
A transistor comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; and a transistor formed in said upper well region.
Claim 13
Dependent Claim
258 words
A transistor comprising: a substrate of a first conductivity type; an epitaxial layer of said first conductivity type formed over a top surface of said substrate, said epitaxial layer having a top surface; a heavily doped buried layer of a second conductivity type formed within said substrate and a lower portion of said epitaxial layer, said buried layer being formed by introducing a first dopant of said second conductivity type into a first region of said substrate, said first dopant being a slow diffusing type dopant; a lower well region of said second conductivity type formed within said substrate and said lower portion of said epitaxial layer and encompassing said buried layer, said lower well region within said epitaxial layer comprising a second dopant of said second conductivity type which has been introduced into said top surface of said substrate, prior to forming said epitaxial layer, and up-diffused into said epitaxial layer, said second dopant of said second conductivity type being a fast diffusing type dopant relative to said first dopant; an upper well region of said second conductivity type formed within an upper portion of said epitaxial layer and merged with said lower well region, said upper well region comprising a dopant of said second conductivity which has been down-diffused into said epitaxial layer so as to merge with said second dopant up-diffused into said epitaxial layer, said upper well region having an impurity concentration which generally decreases with distance from said top surface of said epitaxial layer; and a transistor formed in said upper well region.
Claim 14
Dependent Claim
32 words
The transistor of claim 10 wherein a size and an impurity concentration of said upper well region is such that a breakdown voltage of said transistor is greater than approximately 130 volts.
References Cited (Backward Citations)
US3723199A
Cited
US4032372A
Cited
US4132573A
Cited
JPS5480036A
Cited
US4272307A
Cited
US4260431A
Cited
US4589004A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-06-07 | 1996-12-07 | 1997-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-06-07 | 2000-12-07 | 2001-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-06-07 | 2004-12-07 | 2005-06-08 | $7700.00 | Window Closed / Lapsed |