Semiconductor memory device having memory cells formed in trench and manufacturing method therefor

Claim 2

A semiconductor memory device having a memory cell formed in a trench, comprising: a semiconductor substrate of a first conductivity type and having a major surface, an insulating layer covering a portion of said major surface, a trench in said substrate and insulating layer extending from said major surface and having a sidewall including an upper portion and a lower portion and a bottom wall, the upper portion of said sidewall being formed of said insulating layer, the bottom wall and the lower portion of said sidewall being formed of said semiconductor substrate, a capacitor and a field effect transistor buried in said trench, said capacitor including (a) a first electrode formed in said semiconductor substrate, (b) a dielectric film formed on a surface of said trench so as to be in contact with said first electrode, and (c) a second electrode formed on said dielectric film, said field effect transistor including (a) a semiconductor layer of the first conductivity type formed on the upper portion of said sidewall so as to be separated from said second electrode and the major surface of said substrate, (b) a gate electrode formed, through an insulating film, on a sidewall surface of said semiconductor layer, (c) first and second impurity regions of a second conductivity type formed in said semiconductor layer with said gate electrode provided therebetween, a first connecting conductive layer provided between said second electrode and said first impurity region, insulated from said gate electrode, so as to electrically connect said first impurity region with said second electrode, and a second connecting conductive layer insulated from said semiconductor layer and formed above said gate electrode in said trench to provide electrical connection with said second impurity region, with second connecting conductive layer being insulated from said gate electrode.

Claim 3

A semiconductor memory device according to claim 1, wherein said second electrode includes a conductive layer of the second conductivity type filling the trench portion formed by said bottom wall and said lower portion formed of said semiconductor substrate.

Claim 4

A semiconductor memory device according to claim 1, wherein said first connecting conductive layer includes a conductive layer of the second conductivity type.

Claim 5

A semiconductor memory device according to claim 1, wherein said second connecting conductive layer includes a conductive layer of the second conductivity type.

Claim 6

A semiconductor memory device according to claim 1, wherein said gate electrode includes a rough cylinder-shaped conductive layer portion having an outer peripheral portion near the side surface of said semiconductor layer.

Claim 7

A semiconductor memory device according to claim 1, wherein said gate electrode includes a rough column-shaped conductive layer portion having an outer peripheral portion near the sidewall surface of said semiconductor layer.

Claim 8

A dynamic random access memory, comprising: a semiconductor substrate of a first conductivity type having a major surface, an insulation layer formed on the major surface of said semiconductor substrate, said semiconductor substrate and said insulation layer having a plurality of trenches, said trench extending from said major surface and having a bottom wall formed of said semiconductor substrate and a sidewall including a lower portion formed of said semiconductor substrate and an upper portion formed of said insulation layer, a plurality of word lines formed on said major surface so as to be insulated from said semiconductor substrate and extending in a first direction, a plurality of bit lines formed on said word lines and extending in a second direction intersecting with said first direction, a plurality of memory cells arranged at intersecting portions between said word lines and said bit lines, each of said memory cells including a capacitor and a field effect transistor buried in said trench, said capacitor including: a first electrode formed in said semiconductor substrate, a dielectric film in contact with said first electrode and formed on said bottom wall and said sidewall portion formed of said semiconductor substrate, a second electrode formed on said dielectric film, said field effect transistor including: a semiconductor sidewall layer of the first conductivity type formed on said sidewall portion formed of said insulation layer so as to be separated from said second electrode, a gate electrode formed on a side surface of said semiconductor sidewall layer in said trench with an insulating film interposed therebetween and connected to said word line, first and second impurity regions of a second conductivity type formed in said semiconductor sidewall layer with said gate electrode provided therebetween, a first connecting conductive layer provided between said second electrode and said first impurity region, insulated from said gate electrode, so as to electrically connect said first impurity region with said second electrode, said bit lines each including an interconnection layer portion formed above said gate electrode in said trench, insulated from said semiconductor sidewall layer, a second connecting conductive layer provided between said second impurity region and said interconnection layer portion, insulated from said gate electrode, so as to electrically connect said second impurity region with said interconnection layer portion.

Claim 9

A dynamic random access memory, comprising: a semiconductor substrate of a first conductivity type having a major surface, an insulation layer formed on the major surface of said semiconductor substrate, said semiconductor substrate and said insulation layer having a plurality of trenches, said trench extending from said major surface and having a bottom wall formed of said semiconductor substrate and a sidewall including a lower portion formed of said semiconductor substrate and an upper portion formed of said insulation layer, a plurality of word lines formed on said major surface so as to be insulated from said semiconductor substrate and extending in a first direction, a plurality of bit lines formed on said word lines and extending in a second direction intersecting with said first direction, a plurality of memory cells arranged at intersecting portions between said word lines and said bit lines, each of said memory cells including a capacitor and a field effect transistor buried in said trench, said capacitor including: a first electrode formed in said semiconductor substrate, a dielectric film in contact with said first electrode and formed on said bottom wall and said sidewall portion formed of said semiconductor substrate, a second electrode formed on said dielectric film, said field effect transistor including: a semiconductor sidewall layer of the first conductivity type formed on said sidewall portion formed of said insulation layer so as to be separated from said second electrode, a gate electrode formed on a side surface of said semiconductor sidewall layer in said trench with an insulating film interposed therebetween and connected to said word line, first and second impurity regions of a second conductivity type formed in said semiconductor sidewall layer with said gate electrode provided therebetween, a first connecting conductive layer provided between said second electrode and said first impurity region, insulated from said gate electrode, so as to electrically connect said first impurity region with said second electrode, said bit lines each including an interconnection layer portion formed above said gate electrode in said trench, insulated from said semiconductor sidewall layer, a second connecting conductive layer provided between said second impurity region and said interconnection layer portion, insulated from said gate electrode, so as to electrically connect said second impurity region with said interconnection layer portion.