Patent US5214845A successfully refreshed from Google Patents.
US5214845A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing high speed integrated circuits
Assignee: Micron Technology Inc
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Filing: 1992-05-11
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Granted: 1993-06-01
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Expires: 2012-05-11
Abstract
Abstract This invention creates a high speed semiconductor interconnect system which contains a plurality of signal traces, each in a flexible printed circuit, and each adhesively sandwiched between or adjacent to a flexible ground circuit and a flexible power circuit. The signal, power and ground circuits are stacked in multilayers and are connected to respective lead fingers and respective die circuits by standard, known methods such as TAB or wire bond and encapsulated in a known way. The ground plane and power plane being adjacent to the signal plane reduces the power-ground loop inductance and thus reduces the package noise. By reducing the inductance, the circuit can have a shorter switching time. Also, by adding the ground plane, the power-ground capacitance is increased, which serves to reduce the effect of power supply fluctuations in the system.
Inventors
- 👤 Jerrold L. King
- 👤 Walter L. Moden
- 👤 Chender Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:41
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/20; H10W44/00; H10W44/20; H10W70/00; H10W70/40; H10W70/453; H10W70/464; H10W70/466; H10W70/475; H10W72/071; H10W72/077; H10W72/701; H10W72/251; H10W72/29; H10W72/50; H10W72/531; H10W72/533; H10W72/534; H10W72/541; H10W72/5445; H10W72/551; H10W72/552; H10W72/5525; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/941; H10W72/944; H10W72/9445; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49146; Y10T29/49169; Y10T29/49171
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
479 words
An improved interconnect method for producing high speed integrated circuits, comprising: a) stacking and laminating together in planar relationship and matching configuration with each other, a plurality of multilayered series of flexible electroconductive printed circuits, multilayered series of flexible electroconductive printed circuits, each of selected design, by means of a plurality of adhesive films of suitable composition, one each of which is attached to the bottom of the stack of multilayered series of printed circuits and between each of the multilayers of the series of circuits and with one edge of the bottom layer of adhesive film being attached to the plurality of lead fingers on one side of a lead frame and the opposing edge of the bottom layer of adhesive film being attached to the plurality of lead fingers on the opposing side of the lead frame, with a plurality of die of selected design, each being located between the opposing lead fingers and also attached to the top surface of the die to the bottom layer of adhesive film; b) having each multilayered series of flexible printed circuits contain a plurality of electrical signal plane circuits and a plurality of electrical power plane circuits and a plurality of electrical ground plane circuits, stacked and adhesively attached to each other in alternating order, with each signal plane circuit having attached proximate thereto and combined electrically therewith, externally, in an appropriate manner, a power plane circuit and a ground plane circuit to reduce the power to ground loop inductance and increase the power to ground capacitance of the signal plane circuit, thus reducing circuit noise and switching time and power supply fluctuations in the signal circuits; c) having each multilayered series of flexible printed circuits contain a signal trace circuit with a ground plane circuit and a power plane circuit adhesively attached proximate thereto, with selected points on one end of the signal trace circuit being attached, through appropriate openings in the multilayer flexible circuit, to appropriate lead fingers on the lead frame and attached on the other end to selected points on the attached die and with the proximate ground plane circuit and power plane circuit each being attached, through appropriate openings in the multilayer flexible circuits, to appropriate lead fingers on the lead frame and attached on the other end of the signal trace circuit to selected points on the attached die and with the proximate ground plane circuit and power plane circuit each being attached, through appropriate openings in the multilayer flexible circuits, to appropriate lead finger on the lead frame, thus completing a power to signal to ground system for a particular integrated circuit; and d) encapsulating and trimming and forming the plurality of multilayered series of flexible printed circuits and die and lead frames in proper sequence on other existing equipment and thus completing the improved interconnect method for high speed integrated circuits.
Claim 2
Dependent Claim
479 words
An improved interconnect method for producing high speed integrated circuits, comprising: a) stacking and laminating together in planar relationship and matching configuration with each other, a plurality of multilayered series of flexible electroconductive printed circuits, multilayered series of flexible electroconductive printed circuits, each of selected design, by means of a plurality of adhesive films of suitable composition, one each of which is attached to the bottom of the stack of multilayered series of printed circuits and between each of the multilayers of the series of circuits and with one edge of the bottom layer of adhesive film being attached to the plurality of lead fingers on one side of a lead frame and the opposing edge of the bottom layer of adhesive film being attached to the plurality of lead fingers on the opposing side of the lead frame, with a plurality of die of selected design, each being located between the opposing lead fingers and also attached to the top surface of the die to the bottom layer of adhesive film; b) having each multilayered series of flexible printed circuits contain a plurality of electrical signal plane circuits and a plurality of electrical power plane circuits and a plurality of electrical ground plane circuits, stacked and adhesively attached to each other in alternating order, with each signal plane circuit having attached proximate thereto and combined electrically therewith, externally, in an appropriate manner, a power plane circuit and a ground plane circuit to reduce the power to ground loop inductance and increase the power to ground capacitance of the signal plane circuit, thus reducing circuit noise and switching time and power supply fluctuations in the signal circuits; c) having each multilayered series of flexible printed circuits contain a signal trace circuit with a ground plane circuit and a power plane circuit adhesively attached proximate thereto, with selected points on one end of the signal trace circuit being attached, through appropriate openings in the multilayer flexible circuit, to appropriate lead fingers on the lead frame and attached on the other end to selected points on the attached die and with the proximate ground plane circuit and power plane circuit each being attached, through appropriate openings in the multilayer flexible circuits, to appropriate lead fingers on the lead frame and attached on the other end of the signal trace circuit to selected points on the attached die and with the proximate ground plane circuit and power plane circuit each being attached, through appropriate openings in the multilayer flexible circuits, to appropriate lead finger on the lead frame, thus completing a power to signal to ground system for a particular integrated circuit; and d) encapsulating and trimming and forming the plurality of multilayered series of flexible printed circuits and die and lead frames in proper sequence on other existing equipment and thus completing the improved interconnect method for high speed integrated circuits.
Claim 3
Dependent Claim
63 words
The improved interconnect method of producing high speed integrated circuits of claim 1, wherein: the signal trace circuits within the plurality of multilayered series of flexible electroconductive printed circuits are connected on opposing ends, through appropriate openings in the flexible circuits, by wire bonding to the respective, selected lead fingers on the lead frame and the respective, selected circuit points on the die.
Claim 4
Dependent Claim
23 words
The improved interconnect method for producing high speed integrated circuits of claim 1 wherein the adhesive layer is thermoplastics in nature and composition.
Claim 5
Dependent Claim
23 words
The improved interconnect method for producing high speed integrated circuits of claim 1 wherein the adhesive layer is thermosetting in nature and composition.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-31 | 1996-11-30 | 1997-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-31 | 2000-11-30 | 2001-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-31 | 2004-11-30 | 2005-06-01 | $7700.00 | Window Closed / Lapsed |