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US5214606A
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Non-volatile semiconductor memory and method for driving the same
Assignee: NEC Electronics Corp
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Filing: 1991-07-17
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Granted: 1993-05-25
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Expires: 2011-07-17
Abstract
Abstract In a flash type EEPROM comprising a memory cell matrix, an X decoder and a Y decoder, the X decoder includes a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by an address signal, a depletion N-channel MOS transistor connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a enhancement P-channel MOS transistor connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal. In an erase voltage verify mode, the gate of the depletion N-channel transistor is brought to a low level and the enhancement P-channel MOS transistor is turned off, so that a selected word lines is charged through the depletion N-channel MOS transistor. Accordingly, a voltage of the selected word line is set to a level lower than the voltage supply voltage.
Inventors
- 👤 Kiyokazu Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:10
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/12; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
192 words
A non-volatile semiconductor memory comprising a memory cell matrix composed of a plurality of memory array including a number of memory cells having a floating gate, the memory cell matrix also including a plurality of word lines and a plurality of digit lines, an X decoder receiving a portion of an address for selecting one of the word lines, and a Y decoder receiving another portion of the address for selecting one of the digit lines, the X decoder including a first circuit for charging an output of the first circuit to a voltage when the first circuit is selected by the address, a first MOS transistor of the depletion type connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a second MOS transistor of the enhancement type connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal.
Claim 2
Dependent Claim
192 words
A non-volatile semiconductor memory comprising a memory cell matrix composed of a plurality of memory array including a number of memory cells having a floating gate, the memory cell matrix also including a plurality of word lines and a plurality of digit lines, an X decoder receiving a portion of an address for selecting one of the word lines, and a Y decoder receiving another portion of the address for selecting one of the digit lines, the X decoder including a first circuit for charging an output of the first circuit to a voltage when the first circuit is selected by the address, a first MOS transistor of the depletion type connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a second MOS transistor of the enhancement type connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal.
Claim 3
Dependent Claim
28 words
A non-volatile semiconductor memory claimed in claim 1 wherein the first MOS transistor is of the N-channel type and the second MOS transistor is of the P-channel type.
Claim 4
Independent Claim
264 words
A method for driving a non-volatile semiconductor memory comprising a memory cell matrix composed of a plurality of memory array including a number of memory cells having a floating gate, the memory cell matrix also including a plurality of word lines and a plurality of digit lines, an X decoder receiving a portion of an address for selecting one of the word lines, and a Y decoder receiving another portion of the address for selecting one of the digit lines, the X decoder including a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by the address, a first MOS transistor of the depletion type connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a second MOS transistor of the enhancement type connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal, the method including the steps of, in an erase voltage verify mode, bringing the gate of the first MOS transistor to a low level and bringing the second MOS transistor in an off condition, so that a selected word lines is charged through the first MOS transistor, whereby a voltage of the selected word line is set to a level lower than the voltage supply voltage.
Claim 5
Independent Claim
264 words
A method for driving a non-volatile semiconductor memory comprising a memory cell matrix composed of a plurality of memory array including a number of memory cells having a floating gate, the memory cell matrix also including a plurality of word lines and a plurality of digit lines, an X decoder receiving a portion of an address for selecting one of the word lines, and a Y decoder receiving another portion of the address for selecting one of the digit lines, the X decoder including a first circuit for charging an output of the first circuit to a voltage supply voltage when the first circuit is selected by the address, a first MOS transistor of the depletion type connected between the output node of the first circuit and a corresponding word line and having a gate connected to receive a control voltage, a second circuit for generating a high voltage at an output node of the second circuit at the time of a write mode, and a second MOS transistor of the enhancement type connected between the output node of the second circuit and the corresponding word line and having a gate connected to receive an erase verify signal, the method including the steps of, in an erase voltage verify mode, bringing the gate of the first MOS transistor to a low level and bringing the second MOS transistor in an off condition, so that a selected word lines is charged through the first MOS transistor, whereby a voltage of the selected word line is set to a level lower than the voltage supply voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |