Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers

Claim 2

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of bit lines each connected with a column of said plurality of memory cells, said plurality of bit lines arrayed in bit line pairs and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said bit line pairs formed with cross-points at said dividing points in which bit line locations are interchanged such that the capacitance between a first bit line of each bit line pair and both bit lines of a respective adjacent bit line pair are substantially equal, adjacent bit line pairs each having a number of cross-points which is exactly divisible by two, the capacitance between each bit line of any bit line pair and ground being substantially equal, said bit lines of said bit line pairs having cross-points including parallel portions and intersecting portions, said parallel portions formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 3

A semiconductor memory device in accordance with claim 1, wherein all bit line pairs have the same number of cross points.

Claim 4

A semiconductor memory device in accordance with claim 1, wherein said bit line pairs further include cross-points at points outside said matrix of memory cells.

Claim 5

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of pairs of bit lines each connected with a column of said plurality of memory cells, and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said pairs of bit lines including cross-points at said dividing points and at points at one end of said bit lines in which bit line cross-points are alternately arranged in a row direction such that the capacitance between a first bit line of each bit line pair and the first bit line of a respective adjacent bit line pair and the capacitance between the first bit line of each bit line pair and a second bit line of the respective adjacent bit line pair are substantially equal, each bit line pair having a number of cross-points which is exactly divisible by two, the capacitance between each bit line of any bit line pair and ground being substantially equal; said cross points of said bit lines of said bit line pairs including parallel portions and intersecting portions, said parallel portions being formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 6

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of pairs of bit lines each connected with a column of said plurality of memory cells, and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said pairs of bit lines including cross-points at said dividing points and at points at one end of said bit lines in which bit line cross-points are alternately arranged in a row direction such that the capacitance between a first bit line of each bit line pair and the first bit line of a respective adjacent bit line pair and the capacitance between the first bit line of each bit line pair and a second bit line of the respective adjacent bit line pair are substantially equal, each bit line pair having a number of cross-points which is exactly divisible by two, the capacitance between each bit line of any bit line pair and ground being substantially equal; said cross points of said bit lines of said bit line pairs including parallel portions and intersecting portions, said parallel portions being formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 7

A semiconductor memory device in accordance with claim 4, wherein all bit line pairs have the same number of cross points.

Claim 8

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of bit lines each connected with a column of said plurality of memory cells, said plurality of bit lines arrayed in bit line pairs and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said bit line pairs formed with cross-points at said dividing points in which bit line locations are interchanged such that the capacitance between one bit line of any bit line pair and ground is substantially equal to the capacitance between the other bit line of said any bit line pair and ground, alternate bit line pairs each having a number of cross-points which is exactly divisible by two, the remaining bit line pairs having no cross-points, said bit lines of said bit line pairs having cross-points including parallel portions and intersecting portions, said parallel portions formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 9

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of bit lines each connected with a column of said plurality of memory cells, said plurality of bit lines arrayed in bit line pairs and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said bit line pairs formed with cross-points at said dividing points in which bit line locations are interchanged such that the capacitance between one bit line of any bit line pair and ground is substantially equal to the capacitance between the other bit line of said any bit line pair and ground, alternate bit line pairs each having a number of cross-points which is exactly divisible by two, the remaining bit line pairs having no cross-points, said bit lines of said bit line pairs having cross-points including parallel portions and intersecting portions, said parallel portions formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 10

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of bit lines each connected with a column of said plurality of memory cells, said plurality of bit lines arrayed in bit line pairs and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said bit line pairs formed with cross-points at said dividing points in which bit line locations are interchanged such that the capacitance between one bit line of any bit line pair and ground is substantially equal to the capacitance between the other bit line of said any bit line pair and ground, said bit lines of said bit line pairs having cross-points including parallel portions and intersecting portions, said parallel portions formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.

Claim 11

A semiconductor memory device comprising a plurality of memory cells arrayed in the form of a matrix of rows and columns, a plurality of bit lines each connected with a column of said plurality of memory cells, said plurality of bit lines arrayed in bit line pairs and a plurality of sense amplifiers, each of said sense amplifiers connected to a respective pair of bit lines for detecting and amplifying a potential difference between the bit lines of the respective pair of bit lines, said matrix having a plurality of dividing points, dividing said matrix into portions of substantially equal length along the direction of the length of said bit lines, said bit line pairs formed with cross-points at said dividing points in which bit line locations are interchanged such that the capacitance between one bit line of any bit line pair and ground is substantially equal to the capacitance between the other bit line of said any bit line pair and ground, said bit lines of said bit line pairs having cross-points including parallel portions and intersecting portions, said parallel portions formed in a first layer, said intersecting portions located at said cross points, at least one of the intersecting bit line portions at each cross point comprising an interconnect layer different from said first layer, each of the bit lines of any bit line pair having the same number of interconnect layers.