Polycide gate MOSFET for integrated circuits

Claim 1

A MOS FET integrated circuit device comprising: a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and an uncapped refractory metal silicide layer wherein the chemical formula of the metal silicide is MSi x , where M is a refractory metal and x is between 2.2 and 2.8; a pattern of lightly doped regions in said substrate adjacent to said structures; a nondensified dielectric spacer structure upon the sidewalls of each of said structures and over the adjacent portions of said substrate; a thin thermal silicon dioxide layer over each of said gate electrode structures, said spacer structure and the semiconductor substrate, wherein the thickness of said thermal silicon dioxide layer, at least over the metal silicide layer, is less than or equal to 300 Angstroms, and the source of the silicon in the silicon dioxide layer is said metal silicide layer; a pattern of heavily doped regions in said substrate adjacent to said dielectric spacer structure on the sidewalls of said structures and over the adjacent portions of said substrate which form lightly doped drain source and drain structures of an MOS FET device; and a passivation layer over said structures and appropriate electrical connecting structures thereover to electrically connect said gate electrode structures and source and drain elements to form said integrated circuit device.