Patent US5212411A successfully refreshed from Google Patents.
US5212411A
Expired / Lapsed
US
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Flip-flop circuit having cmos hysteresis inverter
Assignee: Renesas Electronics Corp
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Filing: 1991-12-02
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Granted: 1993-05-18
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Expires: 2011-12-02
Abstract
Abstract A flip-flop circuit includes a hysteresis inverter, a data input terminal, a data output terminal, a clock input terminal and a transfer gate. The hysteresis inverter has a first inverter whose input and output nodes are connected respectively to the data input and output terminals, and a second inverter whose input and output node are connected respectively to the data output and input terminals. The transfer gate is connected between the data input and output terminals, and turns on and off in response to a clock signal applied to the clock input terminal, thereby changing hysteresis area or effects of the hysteresis inverter. The transfer gate causes the area of hysteresis to be variable, so that the circuit requires only a small number of gate stages, can operate at a high speed, and can operate at a low power supply voltage.
Inventors
- 👤 Hiroshi Asazawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:04
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; H03K3/353; H03K3/356; H03K3/356104; H03K3/356165; H03K3/356173; H03K3/3562; H03K3/35625
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
145 words
A master-slave T-type flip-flop circuit comprising: a master stage flip-flop circuit including a master stage hysteresis inverter and a master stage complementary transfer gate circuit connected between input and output nodes of said master stage flip-flop circuit, said master stage complementary transfer gate circuit receiving complementary clock signals; a slave stage flip-flop circuit directly connected in series with said master stage flip-flop circuit and including a slave stage hysteresis inverter and a slave stage complementary transfer gate circuit connected between input and output nodes of said slave stage flip-flop circuit, said slave stage complementary transfer gate circuit receiving said complementary clock signals; an output terminal, said output node of said slave stage flip-flop circuit being connected to said output terminal; and a feedback inverter interconnected between the output node of said slave stage flip-flop circuit and the input node of said master stage flip-flop circuit.
Claim 2
Dependent Claim
145 words
A master-slave T-type flip-flop circuit comprising: a master stage flip-flop circuit including a master stage hysteresis inverter and a master stage complementary transfer gate circuit connected between input and output nodes of said master stage flip-flop circuit, said master stage complementary transfer gate circuit receiving complementary clock signals; a slave stage flip-flop circuit directly connected in series with said master stage flip-flop circuit and including a slave stage hysteresis inverter and a slave stage complementary transfer gate circuit connected between input and output nodes of said slave stage flip-flop circuit, said slave stage complementary transfer gate circuit receiving said complementary clock signals; an output terminal, said output node of said slave stage flip-flop circuit being connected to said output terminal; and a feedback inverter interconnected between the output node of said slave stage flip-flop circuit and the input node of said master stage flip-flop circuit.
Claim 3
Dependent Claim
117 words
A master-slave T-type flip-flop circuit according to claim 1, wherein said master stage hysteresis inverter includes a first inverter having input and output which are connected respectively to the input and output nodes of said master stage flip-flop circuit, and a second inverter having input and output which are connected respectively to the output and input nodes of said master stage flip-flop circuit, and said slave stage hysteresis inverter including a third inverter having input and output which are connected respectively to the input and output nodes of said slave stage flip-flop circuit and a fourth inverter having input and output which are connected respectively to the output an input nodes of said slave stage flip-flop circuit.
Claim 4
Dependent Claim
40 words
A master slave T-type flip-flop circuit according to claim 1, wherein each of said master and slave stage complementary transfer gate circuits includes an N-channel field effect transistor and a P-channel field effect transistor connected in parallel with each other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-17 | 1996-11-16 | 1997-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-17 | 2000-11-16 | 2001-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-17 | 2004-11-16 | 2005-05-18 | $7700.00 | Window Closed / Lapsed |