Method for manufacturing an mos transistor

Claim 1

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring the insulation layer such that said insulating layer has an opening in which the surface of the substrate is exposed; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer; f) forming from the first layer, the second layer and the third layer a channel region of the MOS transistor; g) producing a gate dielectric at the surface of the channel region; h) producing a gate electrode at the surface of the gate dielectric; i) completely covering the gate electrode with an insulating structure; j) forming the insulating structure and the insulation layer of a material such that the first layer, the second layer and the third layer are selectively etchable with respect to the material of the insulting structure and the insulating layer; k) producing depressions extending into the first layer in an anisotropic etching step wherein the insulating structure and the insulation layer act as an etching mask; l) applying surface-wide a glass layer that is provided with a dopant of the second conductivity type; m) forming, in a tempering step, a source region and a drain region by driving the dopant out into surfaces of the first layer, of the second layer and of the third layer having contact with the glass layer; n) managing the tempering step such that dopant distribution in the second layer and in the third layer remains substantially unaltered.

Claim 2

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring the insulation layer such that said insulating layer has an opening in which the surface of the substrate is exposed; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer; f) forming from the first layer, the second layer and the third layer a channel region of the MOS transistor; g) producing a gate dielectric at the surface of the channel region; h) producing a gate electrode at the surface of the gate dielectric; i) completely covering the gate electrode with an insulating structure; j) forming the insulating structure and the insulation layer of a material such that the first layer, the second layer and the third layer are selectively etchable with respect to the material of the insulting structure and the insulating layer; k) producing depressions extending into the first layer in an anisotropic etching step wherein the insulating structure and the insulation layer act as an etching mask; l) applying surface-wide a glass layer that is provided with a dopant of the second conductivity type; m) forming, in a tempering step, a source region and a drain region by driving the dopant out into surfaces of the first layer, of the second layer and of the third layer having contact with the glass layer; n) managing the tempering step such that dopant distribution in the second layer and in the third layer remains substantially unaltered.

Claim 7

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring said insulating layer such that said insulating layer has an opening wherein the surface of said substrate is uncovered and which defines a region for the MOS transistor; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer, the first layer, the second layer and the third layer forming a channel region of the MOS transistor; f) producing a source region and a drain region, each of which is respectively doped of said second conductivity type, at two opposite sides of said channel region; g) producing a gate dielectric at a surface of said channel region; h) producing a gate electrode, at a surface of said gate dielectric; i completely covering the gate electrode with an insulating structure; j forming the insulating layer and the insulating structure of a material such that said first layer, said second layer and said third layer are selectively etchable with respect to said material; k in an anisotropic etching step, which is selective to said insulating layer and said insulating structure, producing depressions extending down to said first layer.

Claim 8

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring said insulating layer such that said insulating layer has an opening wherein the surface of said substrate is uncovered and which defines a region for the MOS transistor; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer, the first layer, the second layer and the third layer forming a channel region of the MOS transistor; f) producing a source region and a drain region, each of which is respectively doped of said second conductivity type, at two opposite sides of said channel region; g) producing a gate dielectric at a surface of said channel region; h) producing a gate electrode, at a surface of said gate dielectric; i completely covering the gate electrode with an insulating structure; j forming the insulating layer and the insulating structure of a material such that said first layer, said second layer and said third layer are selectively etchable with respect to said material; k in an anisotropic etching step, which is selective to said insulating layer and said insulating structure, producing depressions extending down to said first layer.

Claim 14

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring said insulating layer such that said insulating layer has an opening wherein the surface of said substrate is uncovered and which defines a region for the MOS transistor; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer, the first layer, the second layer and the third layer forming a channel region of the MOS transistor; f) producing a source region and a drain region, each of which is respectively doped of said second conductivity type, at two opposite sides of said channel region; g) producing a gate dielectric at a surface of said channel region; h) producing a gate electrode, at a surface of said gate dielectric; i completely covering the gate electrode with an insulating structure; the insulating structure being formed by forming a first insulating layer on the gate electrode, said first insulating layer having sidewalls perpendicular to surface of the substrate shared in common with the gate electrode, and producing sidewall insulations at the sidewalls by surface-wide, conforming depositions and subsequent anisotropic reetching of a second insulating layer; j forming the insulating layer and the insulating structure of a material such that said first layer, said second layer and said third layer are selectively etchable with respect to said material; and k in an anisotropic etching step, which is selective to said insulating layer and said insulating structure, producing depressions extending down to said first layer.

Claim 15

A method for manufacturing an MOS transistor comprising the steps of: a) applying an insulating layer onto a surface of a substrate that is doped with a first conductivity type; b) structuring said insulating layer such that said insulating layer has an opening wherein the surface of said substrate is uncovered and which defines a region for the MOS transistor; c) growing a first layer that is undoped on the surface of the substrate that is exposed inside the opening on the basis of selective epitaxy; d) growing a second layer by selective epitaxy on the first layer, said second layer being doped with the first conductivity type and being thinner than the first layer; e) growing a third layer on the second layer by selective epitaxy, said third layer being doped with a second conductivity type opposite said first conductivity type and being thicker than the second layer, the first layer, the second layer and the third layer forming a channel region of the MOS transistor; f) producing a source region and a drain region, each of which is respectively doped of said second conductivity type, at two opposite sides of said channel region; g) producing a gate dielectric at a surface of said channel region; h) producing a gate electrode, at a surface of said gate dielectric; i completely covering the gate electrode with an insulating structure; the insulating structure being formed by forming a first insulating layer on the gate electrode, said first insulating layer having sidewalls perpendicular to surface of the substrate shared in common with the gate electrode, and producing sidewall insulations at the sidewalls by surface-wide, conforming depositions and subsequent anisotropic reetching of a second insulating layer; j forming the insulating layer and the insulating structure of a material such that said first layer, said second layer and said third layer are selectively etchable with respect to said material; and k in an anisotropic etching step, which is selective to said insulating layer and said insulating structure, producing depressions extending down to said first layer.