Pattern synchronizing circuit

Claim 1

A pattern synchronizing circuit comprising: pre-clock eliminating means for eliminating one clock pulse from a high-speed clock input thereto upon each application thereto of a pre-clock pulse eliminating signal; clock dividing means for frequency dividing the high-speed clock output from said pre-clock eliminating means to 1/N; demultiplexing means for sequentially demultiplexing consecutive bits of high-speed input data into N parallel low-speed sequences on N output lines in synchronization with said high-speed clock and said N sequences of low-speed data are output in synchronization with said frequency divided clock, N being an integer equal to or greater than 2; post-clock pulse eliminating means, supplied with said frequency divided clock, for eliminating one pulse from said frequency divided clock upon each application thereto of a post-clock pulse eliminating signal and outputting an output clock; reference pattern generating means for generating N parallel sequences of reference patterns, sequentially displaced apart in phase, in synchronization with the output clock of said post-clock pulse eliminating means; N comparators, whereby an Nth sequence of low-speed data, composed of data of every Nth bit of N-bit data being sequentially demultiplexed by said demultiplexing means into N parallel sequences and output upon each occurrence of said frequency divided clock is compared with said N parallel sequences of reference patterns, each of said N comparators outputting an agreement or disagreement signal; asynchronism detecting means for generating said post-clock pulse eliminating signal upon detecting that each of said N comparators has output said disagreement signal; and synchronization setting means for detecting one of said N parallel sequences of reference patterns with which an Nth sequence of low-speed data is synchronized and for generating said pre-clock pulse eliminating signals of a number corresponding to a line position of said sequence of reference patterns synchronized with said Nth sequence of low-speed data, whereby line positions of said N parallel sequences of low-speed data are sequentially shifted by said corresponding number in said demultiplexing means so that said Nth sequence of low-speed data assumes the same line position as that of said synchronized reference pattern.