US5210639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual-port memory with inhibited random access during transfer cycles with serial access
Assignee: Texas Instruments Inc
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Filing: 1992-04-10
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Granted: 1993-05-11
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Expires: 2012-04-10
Abstract
Abstract In a video computer system having a dual-port bit-mapped RAM unit incorporating a shift register, provision is made for coupling data between column lines and the shift register, and for simultaneously preventing any column line from being coupled with the random data output terminal of the RAM unit. Accordingly, this prevents two or more different data bits from appearing simultaneously from the RAM unit and causing confusion as to which is the valid signal and which is a spurious signal.
Inventors
- 👤 Donald J. Redwine
- 👤 Raymond Pinkham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:38
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/391; G09G5/363; G09G5/395; G11; G11C; G11C7/00; G11C7/10; G11C7/1075; H; H04; H04N; H04N5/00; H04N5/76; H04N5/907; G09G2360/00; G09G2360/12; G09G2360/126; G09G2360/127
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
350 words
An integral memory device having random and serial access capability, comprising the following elements: an internal array of rows and columns of addressable memory cells; a plurality of address input terminals for receiving an address from external of said memory device; address circuitry for selecting a memory cell in said array responsive to said address input terminals receiving an address; random access input circuitry for writing externally received data to said memory cell selected by said address circuitry; random access output circuitry for accessing the contents of said memory cell selected by said address circuitry and presenting it externally of said memory device; a register comprised of a plurality of memory cells internal of said device; memory transfer circuitry for transferring the contents of selected memory cells of said array into the memory cells of said register; serial output circuitry coupled to at least one memory cell in said register for presenting the contents of said memory cell in said register to external of said device; transfer control circuitry, responsive to a transfer control signal and internal of said device, for selectively enabling and disabling said memory transfer circuitry so that, while said memory transfer circuitry is disabled, data may be randomly written to and read from any of said memory cells in said array independently from the presentation of data by said serial output circuitry; serial transfer circuitry responsive to a serial clock signal for transferring to said serial output circuitry the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented externally of said device by said serial output circuitry; and a buffer circuit, internal of said device, coupled to said random access output circuitry and responsive to said transfer control circuitry, for selectively inhibiting said random access output circuitry from externally presenting the contents of said memory cell selected by said address circuitry during such time as said memory transfer circuitry is enabled; wherein all of said elements are included in said integral memory device,
Claim 2
Dependent Claim
350 words
An integral memory device having random and serial access capability, comprising the following elements: an internal array of rows and columns of addressable memory cells; a plurality of address input terminals for receiving an address from external of said memory device; address circuitry for selecting a memory cell in said array responsive to said address input terminals receiving an address; random access input circuitry for writing externally received data to said memory cell selected by said address circuitry; random access output circuitry for accessing the contents of said memory cell selected by said address circuitry and presenting it externally of said memory device; a register comprised of a plurality of memory cells internal of said device; memory transfer circuitry for transferring the contents of selected memory cells of said array into the memory cells of said register; serial output circuitry coupled to at least one memory cell in said register for presenting the contents of said memory cell in said register to external of said device; transfer control circuitry, responsive to a transfer control signal and internal of said device, for selectively enabling and disabling said memory transfer circuitry so that, while said memory transfer circuitry is disabled, data may be randomly written to and read from any of said memory cells in said array independently from the presentation of data by said serial output circuitry; serial transfer circuitry responsive to a serial clock signal for transferring to said serial output circuitry the contents of another memory cell in said register so that, upon a series of said serial clock signals, the contents of a series of memory cells in said register will be presented externally of said device by said serial output circuitry; and a buffer circuit, internal of said device, coupled to said random access output circuitry and responsive to said transfer control circuitry, for selectively inhibiting said random access output circuitry from externally presenting the contents of said memory cell selected by said address circuitry during such time as said memory transfer circuitry is enabled; wherein all of said elements are included in said integral memory device,
Claim 3
Dependent Claim
58 words
The device of claim 1, wherein said memory cells in said register are serially connected with respect to one another; and wherein said register is coupled to said serial transfer circuitry so that, responsive to said serial clock signal, the contents of each memory cell in said register is shifted to an adjacent memory cell in said register.
Claim 4
Dependent Claim
60 words
The device of claim 2, further comprising: serial input circuitry coupled to at least one memory cell in said register, for writing data into said at least one memory cell; and wherein said memory transfer circuitry is also provided to transfer the contents of said memory cells in said register to a like number of memory cells in said array.
Claim 5
Dependent Claim
57 words
The device of claim 1, wherein said address circuitry comprises: row address circuitry for selecting a row in said array corresponding to a row address received by said address input terminals; and column address circuitry for selecting a column in said selected row, said selected column corresponding to a column address received by said address input terminals.
Claim 6
Dependent Claim
108 words
The device of claim 4, further comprising: address strobe circuitry, coupled to said row address circuitry and responsive to a strobe signal, for enabling said row address circuitry to select the row in said array corresponding to said row address signal being received by said row address circuitry when said strobe signal occurs; and buffer control circuitry connected to said address strobe circuitry and to said transfer control circuitry for controlling said buffer circuit to selectively inhibit said random access output circuitry responsive to said transfer control circuitry receiving said transfer control signal within a predetermined time interval relative to said address strobe circuitry receiving said strobe signal.
Claim 7
Dependent Claim
234 words
A dual-port integral memory device having random and serial access capability, comprising the following elements; an internal array of memory cells; a serial register, internal of said device, coupled to said array of data transfer circuitry and including a serial output coupled to a serial access output terminal; address circuitry, receiving an address from address input terminals, for randomly selecting a single memory cell from said array for random access operation or a plurality of memory cells for serial access operation; random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry; random access output circuitry for presenting the contents of said memory cell selected by said address circuitry to external of said device; a transfer control circuit, coupled to a control terminal providing control signals, to select between serial access operation and random access operation, said control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation; and first output control circuitry internal of said device, coupled to said random access output circuitry and responsive to said control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated; wherein all of said elements are included in said integral memory device.
Claim 8
Dependent Claim
234 words
A dual-port integral memory device having random and serial access capability, comprising the following elements; an internal array of memory cells; a serial register, internal of said device, coupled to said array of data transfer circuitry and including a serial output coupled to a serial access output terminal; address circuitry, receiving an address from address input terminals, for randomly selecting a single memory cell from said array for random access operation or a plurality of memory cells for serial access operation; random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry; random access output circuitry for presenting the contents of said memory cell selected by said address circuitry to external of said device; a transfer control circuit, coupled to a control terminal providing control signals, to select between serial access operation and random access operation, said control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation; and first output control circuitry internal of said device, coupled to said random access output circuitry and responsive to said control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated; wherein all of said elements are included in said integral memory device.
Claim 9
Dependent Claim
16 words
A device according to claim 6, wherein said memory cells are one transistor dynamic memory cells.
Claim 10
Dependent Claim
22 words
A device according to claim 6, wherein said serial register comprises a serial shift register having a number of data storage locations.
Claim 11
Dependent Claim
30 words
A device according to claim 6, wherein the number of said data storage locations is equal to the number of columns of memory cells in said array of memory cells.
Claim 12
Dependent Claim
36 words
A device according to claim 6, further comprising serial clock circuitry for receiving an externally received serial clock signal to transfer a plurality of data bits serially from said serial register to said serial output terminal.
Claim 13
Dependent Claim
114 words
A device according to claim 6, further comprising: address strobe circuitry coupled to said address circuitry and responsive to an externally received strobe signal for enabling said address circuitry to select the memory cell in said array responsive to the external address being received by said address input terminals at the time said strobe signal occurs; and second output control circuitry coupled to said address strobe circuitry and to said transfer control circuit for controlling said first output control circuitry to selectively inhibit said random access output circuitry responsive to said transfer control circuitry receiving a transfer control signal within a predetermined time interval relative to said address strobe circuitry receiving said strobe signal.
Claim 14
Dependent Claim
250 words
A data processing system comprising: a data processing unit; a utilization device utilizing data processed by said data processing unit; and an integral memory device for storing data and having serial and random access capability, the memory device comprising the following elements: an internal array of memory cells; a serial register, internal of said device, coupled to said array by data transfer circuitry and including a serial output coupled to a serial output terminal; address circuitry, receiving an external address from address input terminals, for randomly selecting a single memory cell from said array for random access operation of selecting a plurality of memory cells for serial access operation; random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry; random access output circuitry; a transfer control circuit, coupled to a control terminal, for providing at least one control signal to select between serial access operation and random access operation, said transfer control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation; and first output control circuitry, internal of said device coupled to said random access output circuitry and responsive to said transfer control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated; wherein all of said elements are comprised in said integral memory device.
Claim 15
Dependent Claim
250 words
A data processing system comprising: a data processing unit; a utilization device utilizing data processed by said data processing unit; and an integral memory device for storing data and having serial and random access capability, the memory device comprising the following elements: an internal array of memory cells; a serial register, internal of said device, coupled to said array by data transfer circuitry and including a serial output coupled to a serial output terminal; address circuitry, receiving an external address from address input terminals, for randomly selecting a single memory cell from said array for random access operation of selecting a plurality of memory cells for serial access operation; random access input circuitry for writing externally received data to said single memory cell selected by said address circuitry; random access output circuitry; a transfer control circuit, coupled to a control terminal, for providing at least one control signal to select between serial access operation and random access operation, said transfer control circuit activating said data transfer circuitry for transferring a plurality of data bits between said serial register and said array during serial access operation; and first output control circuitry, internal of said device coupled to said random access output circuitry and responsive to said transfer control circuit for selectively inhibiting said random access output circuitry from externally presenting the contents of said single memory cell selected by said address circuitry while said data transfer circuitry is activated; wherein all of said elements are comprised in said integral memory device.
Claim 16
Dependent Claim
117 words
The system of claim 12, wherein the memory device further comprises: address strobe circuitry coupled to said address circuitry and responsive to an externally received strobe signal for enabling said address circuitry to select the memory cell in said array responsive to the address signal being received by said address input terminals at the time said strobe signal occurs; and second output control circuitry coupled to said address strobe circuitry and to said transfer control circuit for controlling said first output control circuitry to selectively inhibit said random access output circuitry responsive to said transfer control circuitry receiving a transfer control signal within a predetermined time interval relative to said address strobe circuitry receiving said strobe signal.
Claim 17
Dependent Claim
99 words
The system of claim 12 wherein said utilization device is a video display, said video display comprising: an input for receiving data; an output for presenting data in visual format; drive circuitry for enabling a plurality of pixel locations in said visual format of said output responsive to the data received by said input; wherein said serial output is for presenting the contents of a memory cell in said register to said input of said video display; and wherein each pixel location in said visual format is associated with a memory cell in said array of said memory device.
Claim 18
Dependent Claim
91 words
The system of claim 13, wherein said data processing unit comprises: a central processing unit; a graphics processing unit, connected to said central processing unit, to said address input terminals of said memory device, and to said transfer control circuit of said memory device, for presenting said plurality of address signals and said at least one control signal to said memory device responsive to predetermined signals presented by said central processing unit; wherein said random access input circuitry and said random access output circuitry are coupled to said central processing unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |