Method of forming a capacitor

Claim 1

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a selected thickness, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through a mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth which is less than the selected thickness and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thickness; selectively masking polysilicon within the first and second contact openings for definition of a capacitor storage node; anisotropically etching the masked polysilicon layer to substantially completely remove polysilicon from atop the non-perpendicular insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; providing a layer of cell dielectric atop the wafer and over polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.

Claim 2

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a selected thickness, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through a mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth which is less than the selected thickness and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thickness; selectively masking polysilicon within the first and second contact openings for definition of a capacitor storage node; anisotropically etching the masked polysilicon layer to substantially completely remove polysilicon from atop the non-perpendicular insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; providing a layer of cell dielectric atop the wafer and over polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.

Claim 16

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a thickness of from about 12,000 Angstroms to about 18,000 Angstroms, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through the mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth of from about 6,000 Angstroms to about 8,000 Angstroms and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than twice the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thickness, the ratio of the second thickness to the first thickness being from about 5:2 to about 5:1; providing a mask over the polysilicon within the first and second contact openings for definition of a capacitor storage node, the mask being substantially centered over the second contact opening and having a diameter which is greater than the selected diameter of the second contact opening; anisotropically etching the polysilicon to substantially completely remove polysilicon from atop the upper surface of the insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; providing a layer of cell dielectric atop the wafer and over polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.

Claim 17

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a thickness of from about 12,000 Angstroms to about 18,000 Angstroms, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through the mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth of from about 6,000 Angstroms to about 8,000 Angstroms and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than twice the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thickness, the ratio of the second thickness to the first thickness being from about 5:2 to about 5:1; providing a mask over the polysilicon within the first and second contact openings for definition of a capacitor storage node, the mask being substantially centered over the second contact opening and having a diameter which is greater than the selected diameter of the second contact opening; anisotropically etching the polysilicon to substantially completely remove polysilicon from atop the upper surface of the insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; providing a layer of cell dielectric atop the wafer and over polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.

Claim 19

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a selected thickness, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through the mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth which is less than the selected thickness and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thicknesses; selectively masking polysilicon within the first and second contact openings for definition of a capacitor storage node; anisotropically etching the masked polysilicon layer to substantially completely remove polysilicon from atop the upper surface of the insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; isotropically etching the insulating dielectric from beneath the non-perpendicularly angled projecting polysilicon portions; providing a conformal layer of cell dielectric atop the wafer and over and beneath polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.

Claim 20

A method of forming a capacitor on a semiconductor wafer comprising the following steps: providing a layer of insulating dielectric atop the semiconductor wafer to a selected thickness, the insulating layer having an upper surface; providing a mask layer over the layer of insulating dielectric; patterning an aperture of a selected diameter through the mask layer for definition of a contact opening through the insulating dielectric layer to a defined area on the wafer; isotropically etching the insulating dielectric through the aperture to a selected depth which is less than the selected thickness and thereby defining a first contact opening of a selected diameter having non-perpendicular angled ramps extending partially into the layer of insulating dielectric which define a first contact opening base, the selected diameter of the first contact opening at the upper insulating dielectric layer surface being greater than the aperture selected diameter; anisotropically etching the insulating dielectric through the aperture and first contact opening to the defined area on the wafer thereby defining a second contact opening of a selected diameter extending from the first contact opening base to the defined area on the wafer, the second contact opening diameter being substantially equal to the selected diameter of the aperture; non-conformally depositing a layer of polysilicon atop the wafer and to within the first and second contact openings, the non-conformal layer incompletely filling the second contact opening and having a first thickness therein, the non-conformal layer having a second thickness over the insulating dielectric layer upper surface which is greater than the first thickness, the non-conformal layer having a third thickness over at least a portion of the angled ramps which is greater than the first and second thicknesses; selectively masking polysilicon within the first and second contact openings for definition of a capacitor storage node; anisotropically etching the masked polysilicon layer to substantially completely remove polysilicon from atop the upper surface of the insulating dielectric and to leave polysilicon atop the non-perpendicular angled ramp portions to provide non-perpendicularly angled projecting polysilicon portions; isotropically etching the insulating dielectric from beneath the non-perpendicularly angled projecting polysilicon portions; providing a conformal layer of cell dielectric atop the wafer and over and beneath polysilicon remaining in the first and second contact openings; and providing a layer of conductive material atop the cell dielectric layer.