Patent US5206832A successfully refreshed from Google Patents.
US5206832A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1991-07-12
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Granted: 1993-04-27
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Expires: 2011-07-12
Abstract
Abstract A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.
Inventors
- 👤 Yasunori Yamaguchi
- 👤 Jun Miyake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:14
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; H; H04; H04N; H04N5/00; H04N5/76; H04N5/907
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
225 words
A method of selecting a predetermined one of a plurality of operation modes of an internal circuit in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving a selection signal for designating said predetermined one of operation modes, comprising the steps of: setting said column address strobe signal at a logic "low" level; setting said write enable signal at a logic "low" level; setting said selection signal at a predetermined logic level; setting said row address strobe signal at a logic "low" level when said column address strobe signal and said write enable signal are at a logic "low" level and said selection signal is at a predetermined logic level; and detecting the levels of the columns address strobe signal, the write enable signal, the selection signal and the row address strobe signal, and selecting the predetermined one of the operation modes in response to the column address strobe signal being at a logic "low" level, the write enable signal being at the logic "low" level, the selection signal being at the predetermined logic level and the row address strobe signal being at the logic "low" level.
Claim 2
Independent Claim
225 words
A method of selecting a predetermined one of a plurality of operation modes of an internal circuit in an address multiplexed dynamic RAM having at least a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal and a fourth external terminal for receiving a selection signal for designating said predetermined one of operation modes, comprising the steps of: setting said column address strobe signal at a logic "low" level; setting said write enable signal at a logic "low" level; setting said selection signal at a predetermined logic level; setting said row address strobe signal at a logic "low" level when said column address strobe signal and said write enable signal are at a logic "low" level and said selection signal is at a predetermined logic level; and detecting the levels of the columns address strobe signal, the write enable signal, the selection signal and the row address strobe signal, and selecting the predetermined one of the operation modes in response to the column address strobe signal being at a logic "low" level, the write enable signal being at the logic "low" level, the selection signal being at the predetermined logic level and the row address strobe signal being at the logic "low" level.
Claim 3
Dependent Claim
16 words
A method according to claim 1, wherein said fourth external terminal is an address input terminal.
Claim 4
Dependent Claim
134 words
In an address multiplexed dynamic RAM having both a normal operational mode and a setting mode for an internal circuit, a circuit arrangement comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second and third external terminals, for detecting levels of said column address strobe signal, said write enable signal and said row address strobe signal, and for initiating said setting mode in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 5
Dependent Claim
134 words
In an address multiplexed dynamic RAM having both a normal operational mode and a setting mode for an internal circuit, a circuit arrangement comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second and third external terminals, for detecting levels of said column address strobe signal, said write enable signal and said row address strobe signal, and for initiating said setting mode in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 6
Dependent Claim
161 words
In an address multiplexed dynamic RAM having both a normal operational mode and a setting mode for an internal circuit, a circuit arrangement comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; a fourth external terminal for receiving a control signal for said internal circuit and means, coupled to said first, second, third, and fourth external terminals, for detecting levels of said column address strobe signal, said write enable signal, said control signal and said row address strobe signal, and for initiating said setting mode in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said control signal being at a first predetermined logic level when said row address strobe signal is at a transactional logic level corresponding to a falling edge.
Claim 7
Dependent Claim
161 words
In an address multiplexed dynamic RAM having both a normal operational mode and a setting mode for an internal circuit, a circuit arrangement comprising: a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; a fourth external terminal for receiving a control signal for said internal circuit and means, coupled to said first, second, third, and fourth external terminals, for detecting levels of said column address strobe signal, said write enable signal, said control signal and said row address strobe signal, and for initiating said setting mode in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said control signal being at a first predetermined logic level when said row address strobe signal is at a transactional logic level corresponding to a falling edge.
Claim 8
Dependent Claim
18 words
An address multiplexed dynamic RAM according to claim 4, wherein said fourth external terminal is an address terminal.
Claim 9
Dependent Claim
162 words
In a video-RAM device formed on one chip, a circuit arrangement comprising: memory means for storing image data; a plurality of input terminals; masking means for inhibiting predetermined input data applied to said input terminals from being supplied to said memory means on the basis of masking signals; a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second, and third external terminals, for detecting levels of said row address strobe signal, said column address strobe signal, and said write enable signal, and for applying said masking signals to said masking means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 10
Dependent Claim
162 words
In a video-RAM device formed on one chip, a circuit arrangement comprising: memory means for storing image data; a plurality of input terminals; masking means for inhibiting predetermined input data applied to said input terminals from being supplied to said memory means on the basis of masking signals; a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second, and third external terminals, for detecting levels of said row address strobe signal, said column address strobe signal, and said write enable signal, and for applying said masking signals to said masking means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 11
Dependent Claim
221 words
A semiconductor memory device used for image processing comprising: a memory for storing image data, wherein said memory includes means to allow a plurality of image data stored therein to be rewritten; an operation circuit coupled to receive input data applied to input terminals and output data read out from said memory, wherein said operation circuit includes means for performing a logical operation based on said input and output data to form operation image data to be written into said memory; a bypass circuit coupled to said input terminals and said memory; a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second and third external terminals, for detecting levels of said column address strobe signal, said write enable signal, and said row address strobe signal, and for controlling said bypass circuit to bypass the operation circuit so that input data can be applied from the input terminals to the memory in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 12
Dependent Claim
221 words
A semiconductor memory device used for image processing comprising: a memory for storing image data, wherein said memory includes means to allow a plurality of image data stored therein to be rewritten; an operation circuit coupled to receive input data applied to input terminals and output data read out from said memory, wherein said operation circuit includes means for performing a logical operation based on said input and output data to form operation image data to be written into said memory; a bypass circuit coupled to said input terminals and said memory; a first external terminal for receiving a row address strobe signal; a second external terminal for receiving a column address strobe signal; a third external terminal for receiving a write enable signal; and means, coupled to said first, second and third external terminals, for detecting levels of said column address strobe signal, said write enable signal, and said row address strobe signal, and for controlling said bypass circuit to bypass the operation circuit so that input data can be applied from the input terminals to the memory in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-26 | 1996-10-26 | 1997-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-26 | 2000-10-26 | 2001-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-26 | 2004-10-26 | 2005-04-27 | $7700.00 | Window Closed / Lapsed |