US5068829A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1990-08-21
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Granted: 1991-11-26
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Expires: 2010-08-21
Abstract
Abstract A semiconductor memory device is provided with a memory portion, a logical operation circuit which receives the data signal read out from such memory portion and the input data signal to form data to be offered to such memory portion, and a gate circuit. In case a data input operation is required which eliminates the logical operation, the input data signal is fed not via the long logical operation circuit, but via the gate circuit directly to the memory portion. The semiconductor memory device constructed as above permits a high speed operation and is suited for use as the memory for image processing.
Inventors
- 👤 Yasunori Yamaguchi
- 👤 Jun Miyake
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:00
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/907; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
188 words
A microprocessor system comprising: a microprocessor for processing image data; and a semiconductor memory coupled to said microprocessor, wherein said semiconductor memory comprises: a memory portion for storing image data, a logic circuit coupled to said memory portion and having a plurality of operation modes which are respectively selected on the basis of a mode selecting signal, control means coupled to said logic circuit for controlling said logic circuit, a first external terminal coupled to said control means for receiving a row address strobe signal, a second external terminal coupled to said control means for receiving a column address strobe signal, a third external terminal coupled to said control means for receiving a write enable signal, and a fourth external terminal coupled to said control means for receiving said mode selecting signal, wherein a predetermined one of said operation modes is selected by said control means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 2
Dependent Claim
188 words
A microprocessor system comprising: a microprocessor for processing image data; and a semiconductor memory coupled to said microprocessor, wherein said semiconductor memory comprises: a memory portion for storing image data, a logic circuit coupled to said memory portion and having a plurality of operation modes which are respectively selected on the basis of a mode selecting signal, control means coupled to said logic circuit for controlling said logic circuit, a first external terminal coupled to said control means for receiving a row address strobe signal, a second external terminal coupled to said control means for receiving a column address strobe signal, a third external terminal coupled to said control means for receiving a write enable signal, and a fourth external terminal coupled to said control means for receiving said mode selecting signal, wherein a predetermined one of said operation modes is selected by said control means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 3
Dependent Claim
17 words
A microprocessor system according to claim 1, wherein said fourth external terminal is an address input terminal.
Claim 4
Dependent Claim
31 words
A microprocessor system according to claim 2, wherein the data to be provided to said memory portion in each operation mode is determined on the basis of said mode selecting signal.
Claim 5
Dependent Claim
219 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a fourth external terminal for receiving a mode selecting signal, a fifth external terminal for receiving input data, a memory portion for storing data, a logic portion coupled to said memory portion and having means for performing a logic operation selected by said mode selecting signal based on said input data and output data read out from said memory portion to form said data to be written into said memory portion, and control means coupled to said first external terminal, said second external terminal, said third external terminal, said fourth external terminal and said logic portion for controlling said logic portion, wherein said logic operation is selected in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said mode selecting signal being at a predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 6
Dependent Claim
219 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a fourth external terminal for receiving a mode selecting signal, a fifth external terminal for receiving input data, a memory portion for storing data, a logic portion coupled to said memory portion and having means for performing a logic operation selected by said mode selecting signal based on said input data and output data read out from said memory portion to form said data to be written into said memory portion, and control means coupled to said first external terminal, said second external terminal, said third external terminal, said fourth external terminal and said logic portion for controlling said logic portion, wherein said logic operation is selected in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said mode selecting signal being at a predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 7
Dependent Claim
17 words
A microprocessor system according to claim 4, wherein said fourth external terminal is an address input terminal.
Claim 8
Dependent Claim
186 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory coupled to said microprocessor, wherein said semiconductor memory comprises: a memory portion for storing data, an internal circuit coupled to said memory portion and having a plurality of operation modes which are respectively selected on the basis of a mode selecting signal, control means coupled to said internal circuit for controlling said internal circuit, a first external terminal coupled to said control means for receiving a row address strobe signal, a second external terminal coupled to said control means for receiving a column address strobe signal, a third external terminal coupled to said control means for receiving a write enable signal, and a fourth external terminal coupled to said control means for receiving said mode selecting signal, wherein a predetermined one of said operation modes is selected by said control means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 9
Dependent Claim
186 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory coupled to said microprocessor, wherein said semiconductor memory comprises: a memory portion for storing data, an internal circuit coupled to said memory portion and having a plurality of operation modes which are respectively selected on the basis of a mode selecting signal, control means coupled to said internal circuit for controlling said internal circuit, a first external terminal coupled to said control means for receiving a row address strobe signal, a second external terminal coupled to said control means for receiving a column address strobe signal, a third external terminal coupled to said control means for receiving a write enable signal, and a fourth external terminal coupled to said control means for receiving said mode selecting signal, wherein a predetermined one of said operation modes is selected by said control means in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 10
Dependent Claim
17 words
A microprocessor system according to claim 6, wherein said fourth external terminal is an address input terminal.
Claim 11
Dependent Claim
31 words
A microprocessor system according to claim 7, wherein the data to be provided to said memory portion in each operation mode is determined on the basis of said mode selecting signal.
Claim 12
Dependent Claim
128 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a memory portion for storing data, and an internal circuit having a plurality of operation modes, wherein one of said plurality of operation modes is selected in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 13
Dependent Claim
128 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a memory portion for storing data, and an internal circuit having a plurality of operation modes, wherein one of said plurality of operation modes is selected in response to said column address strobe signal being at a logic "low" level and said write enable signal being at a logic "low" level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 14
Dependent Claim
147 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a fourth external terminal for receiving a mode selecting signal, a memory portion for storing data, and an internal circuit having a plurality of operation modes, wherein one of said plurality of operation modes is selected in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said selecting signal being at a predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 15
Dependent Claim
147 words
A microprocessor system comprising: a microprocessor for processing data; and a semiconductor memory device coupled to said microprocessor, wherein a circuit arrangement of said semiconductor memory device comprises: a first external terminal for receiving a row address strobe signal, a second external terminal for receiving a column address strobe signal, a third external terminal for receiving a write enable signal, a fourth external terminal for receiving a mode selecting signal, a memory portion for storing data, and an internal circuit having a plurality of operation modes, wherein one of said plurality of operation modes is selected in response to said column address strobe signal being at a logic "low" level, said write enable signal being at a logic "low" level and said selecting signal being at a predetermined logic level when said row address strobe signal is at a transitional logic level corresponding to a falling edge.
Claim 16
Dependent Claim
17 words
A microprocessor system according to claim 10, wherein said fourth external terminal is an address input terminal.
References Cited (Backward Citations)
US4347587A
Cited
JPS5960658A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-25 | 1995-05-27 | 1995-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-25 | 1999-05-27 | 1999-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-25 | 2003-05-27 | 2003-11-26 | $7700.00 | Window Closed / Lapsed |