Compound semiconductor field effect transistor having a gate insulator formed of insulative superlattice layer

Claim 2

A field effect transistor comprising an InGaAs current channel layer, a source electrode and a drain electrode formed on said current channel layer separately from each other and in ohmic contact with said current channel layer, an insulator layer formed above and in contact with said current channel layer between said source electrode and said drain electrode, and a gate electrode formed above and in contact with said insulator layer, said insulator layer being composed of a superlattice layer formed of alternately stacked undoped InAs thin films and undoped AlAs thin films, a ratio t 1 /t 2 of the thickness t 1 of each one InAs thin film and the thickness t 2 of one AlAs thin film adjacent to said each one InAs thin film being gradually reduced toward an upper surface of said superlattice layer.

Claim 3

A field effect transistor claimed in claim 1 wherein said InGaAs current channel layer is formed of In 0 .53 Ga 0 .47 As and wherein a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said current channel layer has said ratio t 1 /t 2 of thickness equal to about 1.08.

Claim 4

A field effect transistor claimed in claim 2 wherein a lowermost InAs thin film included in said superlattice layer has a thickness of about 52 Å and a lowermost AlAs thin film included in said superlattice layer has a thickness of about 48 Å.

Claim 5

A field effect transistor claimed in claim 3 wherein a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said gate electrode has said ratio t 1 /t 2 of thickness substantially equal to 0.0064.

Claim 6

A field effect transistor claimed in claim 4 wherein said gate electrode is formed of a metal which forms a Schottky barrier between said gate electrode and said superlattice layer.

Claim 7

A field effect transistor claimed in claim 5 wherein each pair consisting of an upper InAs thin film and an adjacent lower AlAs thin film included in said superlattice layer has a total thickness of about 100 Å.

Claim 8

A field effect transistor claimed in claim 6 wherein said superlattice layer includes at least ten layers of said InAs thin films and at least ten layers of said AlAs thin films.

Claim 9

A field effect transistor claimed in claim 4 wherein said current channel layer is formed on a buffer layer formed on a semi-insulative InP substrate.

Claim 10

A field effect transistor claimed in claim 8 wherein said buffer layer is formed of InAlAs.

Claim 11

A field effect transistor claimed in claim 8 wherein said buffer layer is formed of a high resistance InP.

Claim 12

A field effect transistor comprising an In 0 .53 Ga 0 .47 As current channel layer, a source electrode and a drain electrode formed on said current channel layer separately from each other and in ohmic contact with said current channel layer, an insulator layer formed above and in contact with said current channel layer between said source electrode and said drain electrode, and a gate electrode formed above and in contact with said insulator layer, said insulator layer being composed of a superlattice layer formed of alternately stacked undoped InAs thin films and undoped AlAs thin films, a ratio t 1 /t 2 of the thickness t 1 of each one InAs thin film and the thickness t 2 of one AlAs thin film adjacent to said each one InAs thin film being gradually reduced toward an upper surface of said superlattice layer in such a manner that a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said current channel layer has said ratio t 1 /t 2 of thickness equal to about 1.08, and a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said gate electrode has said ratio t 1 /t 2 of thickness substantially equal to 0.0064.

Claim 13

A field effect transistor comprising an In 0 .53 Ga 0 .47 As current channel layer, a source electrode and a drain electrode formed on said current channel layer separately from each other and in ohmic contact with said current channel layer, an insulator layer formed above and in contact with said current channel layer between said source electrode and said drain electrode, and a gate electrode formed above and in contact with said insulator layer, said insulator layer being composed of a superlattice layer formed of alternately stacked undoped InAs thin films and undoped AlAs thin films, a ratio t 1 /t 2 of the thickness t 1 of each one InAs thin film and the thickness t 2 of one AlAs thin film adjacent to said each one InAs thin film being gradually reduced toward an upper surface of said superlattice layer in such a manner that a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said current channel layer has said ratio t 1 /t 2 of thickness equal to about 1.08, and a pair of adjacent thin films which consists of one InAs thin film and one AlAs thin film and is adjacent to said gate electrode has said ratio t 1 /t 2 of thickness substantially equal to 0.0064.

Claim 14

A field effect transistor claimed in claim 11 wherein a lowermost InAs thin film included in said superlattice layer has a thickness of about 52 Å and a lowermost AlAs thin film included in said superlattice layer has a thickness of about 48 Å.

Claim 15

A field effect transistor claimed in claim 11 wherein said current channel layer is formed on a buffer layer formed on a semi-insulative InP substrate.

Claim 16

A field effect transistor claimed in claim 13 wherein said buffer layer is formed of In 0 .52 Al 0 .48 As.

Claim 17

A field effect transistor claimed in claim 13 wherein said buffer layer is formed of a high resistance InP.