EP0202755A1
Expired / Lapsed
EP
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Double heterojunction field effect transistor data storage device
Assignee: International Business Machines Corp
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Filing: 1986-04-11
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Granted: —
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Expires: 2006-04-11
Abstract
Abstract Reversible control of conduction in a band offset heterojunction field effect transistor device is achieved by an asymmetric barrier (10) which can position a potential well across the Fermi level to produce conduction and away from the Fermi level for a non-conducting condition and to retain that position in the absence of a signal. The device can be a GaAs channel FET with a multilayer gate comprising, in order of proximity to the GaAs channel, a gate layer (3) of GaA1As, a charge storage layer (8) of GaAs, an asymmetric barrier layer (10) of GaA1As graded towards the GaAs storage layer and an ohmic adapting layer (13) of GaAs.
Inventors
- 👤 John Lawrence Freeouf
- 👤 Thomas Nelson Jackson
- 👤 Peter Daniel Kirchner
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 11:53
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D30/00; H10D30/80; H10D30/801; H10D30/803
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
156 words
A double heterojunction field effect transistor data storage device comprising a substrate (1) of single crystal semiconductor material having disposed therein spaced apart source and drain regions (4.5) defining a channel region there-between, a gate layer (3) of single crystal semiconductor material which has a larger bandgap than that of the substrate, forming a heterojunction (2) with the substrate and disposed over the channel region, a charge storage layer (8) of semiconductor material forming a heterojunction (9) with the gate layer and disposed over the channel region, the energy band difference between the gate and charge storage layers being substantially equal to that between the substrate and the gate layer charge transfer means (10), having an asymmetric charge transfer characteristic, contiguous with the face of the charge storage layer opposite to that forming the heterojunction (9) with the gate layer and charge introduction and removal means - (13,15) contiguous with the charge transfer means - (10).
Claim 2
Dependent Claim
156 words
A double heterojunction field effect transistor data storage device comprising a substrate (1) of single crystal semiconductor material having disposed therein spaced apart source and drain regions (4.5) defining a channel region there-between, a gate layer (3) of single crystal semiconductor material which has a larger bandgap than that of the substrate, forming a heterojunction (2) with the substrate and disposed over the channel region, a charge storage layer (8) of semiconductor material forming a heterojunction (9) with the gate layer and disposed over the channel region, the energy band difference between the gate and charge storage layers being substantially equal to that between the substrate and the gate layer charge transfer means (10), having an asymmetric charge transfer characteristic, contiguous with the face of the charge storage layer opposite to that forming the heterojunction (9) with the gate layer and charge introduction and removal means - (13,15) contiguous with the charge transfer means - (10).
Claim 3
Dependent Claim
24 words
A device as claimed in claim 1, in which the charge transfer means consists of a layer of a graded band gap semiconductor material.
Claim 4
Dependent Claim
18 words
A device as claimed in claim 1, in which the charge transfer means consists of a tunnelling barrier.
Claim 5
Independent Claim
28 words
A device as claimed in any preceding claim, in which the charge introduction and removal means comprises an epitaxial layer of semiconductor material contacting the charge transfer means.
Claim 6
Dependent Claim
31 words
A device as claimed in Claim 2 in which the substrate and the charge storage layer are of GaAs and the gate layer and the charge transfer means are of CaA1As.
Claim 7
Dependent Claim
34 words
A device as claimed in claim 5, in which the signal introduction and removal means comprises an epitaxial layer of GaAs contacting the charge transfer layer and an ohmic contact contacting that GaAs layer.
References Cited (Backward Citations)
EP0114962A2
Cited
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