Method of forming a bit line over capacitor array of memory cells

Claim 1

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide and within the buried contacts; providing a second layer of polyimide atop the wafer to a selected thickness over the first layer of conductively doped polysilicon, the second layer of polyimide having a substantially planar upper surface; etching the second layer of polyimide and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions; providing a third layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes; patterning and etching the third and first layers of polyimide to define bit line contact openings to the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first, second and third layers of polyimide from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 2

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide and within the buried contacts; providing a second layer of polyimide atop the wafer to a selected thickness over the first layer of conductively doped polysilicon, the second layer of polyimide having a substantially planar upper surface; etching the second layer of polyimide and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions; providing a third layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes; patterning and etching the third and first layers of polyimide to define bit line contact openings to the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first, second and third layers of polyimide from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 14

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide and within the buried contacts; providing a layer of material which is selectively etchable relative to polysilicon atop the wafer to a selected thickness over the first layer of conductively doped polysilicon; etching the layer of material and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions; providing a second layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes and remaining layer of material; patterning and etching the second and first layers of polyimide to define bit line contact openings to the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first and second layers of polyimide and layer of material from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 15

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide and within the buried contacts; providing a layer of material which is selectively etchable relative to polysilicon atop the wafer to a selected thickness over the first layer of conductively doped polysilicon; etching the layer of material and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions; providing a second layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes and remaining layer of material; patterning and etching the second and first layers of polyimide to define bit line contact openings to the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first and second layers of polyimide and layer of material from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 23

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of a first material atop the wafer to a selected thickness, the first material being selectively etchable relative to oxide and polysilicon; patterning and etching the layer of first material to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned layer of first material and within the buried contacts; providing a layer of second material atop the wafer to a selected thickness over the first layer of conductively doped polysilicon, the second material being selectively etchable relative to oxide and polysilicon; etching the layer of second material and first layer of polysilicon over the patterned layer of first material to define isolated cell storage nodes which contact the first active regions; providing a layer of third material atop the wafer to a selected thickness over the isolated cell storage nodes and remaining layer of second material, the third material being selectively etchable relative to oxide and polysilicon; patterning and etching the layers of third and first material to define bit line contact openings to the second active regions; providing insulating spacers of oxide within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the oxide insulation spacers therewithin, the pillars being surrounded by the oxide insulating spacers; etching remaining portions of the layers of first, second and third materials from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 24

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a layer of a first material atop the wafer to a selected thickness, the first material being selectively etchable relative to oxide and polysilicon; patterning and etching the layer of first material to define buried contact openings to the first active regions; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned layer of first material and within the buried contacts; providing a layer of second material atop the wafer to a selected thickness over the first layer of conductively doped polysilicon, the second material being selectively etchable relative to oxide and polysilicon; etching the layer of second material and first layer of polysilicon over the patterned layer of first material to define isolated cell storage nodes which contact the first active regions; providing a layer of third material atop the wafer to a selected thickness over the isolated cell storage nodes and remaining layer of second material, the third material being selectively etchable relative to oxide and polysilicon; patterning and etching the layers of third and first material to define bit line contact openings to the second active regions; providing insulating spacers of oxide within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the oxide insulation spacers therewithin, the pillars being surrounded by the oxide insulating spacers; etching remaining portions of the layers of first, second and third materials from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 33

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of nitride atop the word lines to a thickness of from about 100 Angstroms to about 500 Angstroms; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the second active regions; providing a second layer of nitride atop the patterned and etched first layer of polyimide to a thickness of from about 100 Angstroms to about 500 Angstroms; anisotropically etching the second layer of nitride to provide nitride spacers about the patterned and etched first layer of polyimide; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide having nitride spacers and within the buried contacts; providing a third layer of nitride to a selected thickness over the first layer of conductively doped polysilicon; etching the third layer of nitride and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions, the buried contact openings laterally overlapping adjacent word lines elevationally above adjacent word lines; providing a second layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes and remaining third layer of nitride; patterning and etching the second and first layers of polyimide to define bit line contact openings to the second active regions, the bit line contact openings laterally overlapping adjacent word lines elevationally above adjacent word lines, the bit line contact openings overlapping with adjacent buried contact openings, the isolated storage nodes projecting into the bit line contact openings; providing insulating oxide about the portions of the storage nodes projecting into the bit line contact openings; etching the first layer of nitride to expose the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first and second layers of polyimide and third layer of nitride from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.

Claim 34

A method of forming a bit line over capacitor array of memory cells comprising: providing an array of substantially electrically isolated word lines atop a semiconductor wafer; providing active areas about the word lines to define an array of memory cell FETs, the active areas being defined by a first active region for electrical connection with a memory cell capacitor and a second active region for electrical connection with a bit line; providing a first layer of nitride atop the word lines to a thickness of from about 100 Angstroms to about 500 Angstroms; providing a first layer of polyimide atop the wafer to a selected thickness, the first layer of polyimide having a substantially planar upper surface; patterning and etching the first layer of polyimide to define buried contact openings to the second active regions; providing a second layer of nitride atop the patterned and etched first layer of polyimide to a thickness of from about 100 Angstroms to about 500 Angstroms; anisotropically etching the second layer of nitride to provide nitride spacers about the patterned and etched first layer of polyimide; providing a first layer of conductively doped polysilicon to a selected thickness atop the wafer over the patterned first layer of polyimide having nitride spacers and within the buried contacts; providing a third layer of nitride to a selected thickness over the first layer of conductively doped polysilicon; etching the third layer of nitride and first layer of polysilicon over the patterned first layer of polyimide to define isolated cell storage nodes which contact the first active regions, the buried contact openings laterally overlapping adjacent word lines elevationally above adjacent word lines; providing a second layer of polyimide atop the wafer to a selected thickness over the isolated cell storage nodes and remaining third layer of nitride; patterning and etching the second and first layers of polyimide to define bit line contact openings to the second active regions, the bit line contact openings laterally overlapping adjacent word lines elevationally above adjacent word lines, the bit line contact openings overlapping with adjacent buried contact openings, the isolated storage nodes projecting into the bit line contact openings; providing insulating oxide about the portions of the storage nodes projecting into the bit line contact openings; etching the first layer of nitride to expose the second active regions; providing insulating spacers within the bit line contact openings; providing conductive material pillars within the bit line contact openings having the insulating spacers therewithin, the pillars being surrounded by the insulating spacers; etching remaining portions of the first and second layers of polyimide and third layer of nitride from the wafer; providing a capacitor cell dielectric layer atop the individual storage nodes; providing a capacitor cell polysilicon layer atop the capacitor cell dielectric layer to define an array of memory cell capacitors; providing an insulating layer atop the cell polysilicon layer; and providing an array of digit lines atop the wafer which electrically connect with the conductive material pillars elevationally above the cell capacitors.