Addition apparatus having round-off function

Claim 2

An addition apparatus having a round-off function for adding together first and second input binary numbers (A24 to A0, B24 to B0) and executing round-off processing of a result of an addition performed thereby, comprising: a first circuit section (P1) including n parallel adders (101, 102) where n is a fixed plural integer, each parallel adder coupled to add together respective first portions (A3 to A0, B3 to B0) of said input numbers, each said first portion of said input numbers comprising a fixed number of bits extending from and including a bit (A0, B0) corresponding to a normalized least significant bit position of said input numbers, said parallel adders being operable for executing round-off addition at n respectively different bit positions (A1, A0), and said parallel adders generating n respective carry output signals which are outputted from said first circuit section as respective section carry output signals (C100, C101), said first circuit section further including data selector means controllable for selecting one out of n respective sets of bits constituting sum results produced from said n parallel adders of the first circuit section and for outputting the selected set of bits constituting one of the sum results (S3 to S0); a plurality of intermediate circuit sections (P2, P3, P4) coupled to receive respective pairs of intermediate numeral portions (A7 to A4, B7 to B4, . . . A18 to A13, B18 to B13) of said input numbers, said pairs of intermediate numeral portions successively increasing in significance above said first portions, each intermediate circuit section of said plurality of intermediate circuit sections including a first parallel adder (103) for adding together a pair of intermediate numeral portions supplied to said intermediate circuit section while fixedly adding a "1" state input carry thereto, and a second parallel adder (104) for adding together the pair of numeral portions supplied to said intermediate circuit section while fixedly adding a "0" state input carry thereto, data selector means (112) controllable for selecting one out of 2 respective sets of bits constituting sum results produced from said first and second parallel adders (103, 104) of said intermediate circuit section and for outputting the selected set of bits constituting said sum result (S7 to S4), carry selector means (120) operable for selecting one out of n carry signals supplied from a preceding one of said circuit sections and for applying the selected carry signal to control said data selector means (112), and n section carry generating circuits each receiving respective carry output signals produced from said first and second parallel adders (103, 104) and a corresponding one of n carry output signals produced from a preceding one of said circuit sections, for generating n respective carry output signals; and a final circuit section coupled to receive respective most significant portions (A24 to A19, B24 to B19) of said input numbers, including a first parallel adder (109) for adding together said most significant portions while fixedly adding a "1" state input carry thereto, and a second parallel adder (110) for adding together said most significant portions while fixedly adding a "0" state input carry thereto, data selector means (115) controllable for selecting one out of 2 respective sets of bits each constituting a carry bit (S 1 25 , S 0 25 ) and sum result (S 1 24 , S 0 24 to S 1 19 , S 0 19 ) produced from said first and second parallel adders (109, 110) of said final circuit section and for outputting the selected set of bits (S25 to S19), carry selector means (123) operable for selecting one out of n carry signals (C112, C113) supplied from a preceding one of said circuit sections and for applying a selected carry signal to control said data selector means (115), and round-off position setting circuit means (140) coupled to receive said n carry signals (C112, C113) supplied from the preceding one of said circuit sections and to receive respective most significant bits (S 1 25 , S 0 25 ) that are produced as carry output from said first and second parallel adders (109, 110) of said final circuit section, and including logic circuit means responsive to a combination of logic states of said input carry signals (C112, C113) and most significant bits for producing corresponding output signals (S100) for controlling said respective data selector means and said carry selection means of said circuit sections, to thereby determine a position at which round-off processing has been executed, to thereby obtain an output result formed of the output bits (S25 to S0) produced from all of said data selector means.

Claim 3

An addition apparatus according to claim 1 wherein said first circuit section, said plurality of intermediate circuit sections and said final circuit section in combination comprise means for executing a round-off process during an addition of two binary values, independently of additional circuitry for executing the round-off process.

Claim 4

In a multiplier apparatus for multiplying together first and second input binary numbers (720, 730), including circuit means (704, 705) for operating on data values respectively representing said input numbers to generate first and second partial products (707A, 707B) each having a most significant bit (A25, B25) that is one bit higher in significance than a most significant bit position (A24, B24) of said input numbers, an addition apparatus having a round-off function for adding together and executing round-off processing of a result of the addition, comprising: a first circuit section (P1) including n parallel adders where n is a fixed integer, each parallel adder coupled to add together respective first portions (A3 to A0, B3 to B0) of said partial products each said first portion of said partial products comprising a fixed number of bits extending from and including a bit (A0, B0) at a least significant bit position of said partial products, said parallel adders being operable for executing round-off addition at n respectively different bit positions (Al, A0), and said parallel adders generating n respective carry output signals which are outputted from said first circuit section as respective section carry output signals (C100, C101), said first circuit section further including data selector means controllable for selecting one out of n respective sets of bits constituting sum results produced from said n parallel adders of the first circuit section and for outputting the selected set of bits constituting one of the sum results (S3 to S0); a plurality of intermediate circuit sections (P2, P3, P4) coupled to receive respective pairs of intermediate numeral portions (A7 to A4, B7 to B4, . . . A18 to A13, B18 to B13) of said partial products, said pairs of intermediate numeral portions successively increasing in significance above said first portions, each intermediate circuit section of said plurality of intermediate circuit sections including a first parallel adder for adding together a pair of intermediate numeral portions supplied to said intermediate circuit section while fixedly adding a "1" state input carry thereto, and a second parallel adder for adding together the pair of numeral portions supplied to said intermediate circuit section while fixedly adding a "0" state input carry thereto, data selector means controllable for selecting one out of 2 respective sets of bits constituting sum results produced from said first and second parallel adders of said intermediate circuit section and for outputting the selected set of bits constituting said sum result (S7 to S4), carry selector means (120) operable for selecting one cut of n carry signals supplied from a preceding one of said circuit sections and for applying the selected carry signal to control said data selector means, and n section carry generating circuits each receiving respective carry output signals produced from said first and second parallel adders and a corresponding one of n carry output signals produced from a preceding one of said circuit sections, for generating n respective carry output signals; and a final circuit section coupled to receive respective most significant portions (A25 to A19, B25 to B19) of said partial products, including a first parallel adder for adding together said most significant portions while fixedly adding a "1" state input carry thereto, and a second parallel adder for adding together said most significant portions while fixedly adding a "0" state input carry thereto, data selector means controllable for selecting one out of 2 respective sets of bits constituting sum results produced from sadi first and second parallel adders of said final circuit section and for outputting the selected sum result (S25 to S19), carry selector means operable for selecting one out of n carry signals supplied from a preceding one of said circuit sections and for applying a selected carry signal to control said data selector means, and round-off position setting circuit means coupled to receive said n carry signals supplied from the preceding one of said circuit sections and to receive said most significant bits (S 1 25 , S 0 25 ) respectively produced from said first and second parallel adders of said final circuit section, and including logic circuit means responsive to a combination of logic states of said input carry signals (C112, C113) and most significant bits for producing corresponding output signals for controlling said respective data selector means and said carry selection means of said circuit sections, to thereby determine a position at which round-off processing has been executed, to thereby obtain an output result formed of the output bits (S25 to S0) produced from all of said data selector means.

Claim 5

In a multiplier apparatus for multiplying together first and second input binary numbers (720, 730), including circuit means (704, 705) for operating on data values respectively representing said input numbers to generate first and second partial products (707A, 707B) each having a most significant bit (A25, B25) that is one bit higher in significance than a most significant bit position (A24, B24) of said input numbers, an addition apparatus having a round-off function for adding together and executing round-off processing of a result of the addition, comprising: a first circuit section (P1) including n parallel adders where n is a fixed integer, each parallel adder coupled to add together respective first portions (A3 to A0, B3 to B0) of said partial products each said first portion of said partial products comprising a fixed number of bits extending from and including a bit (A0, B0) at a least significant bit position of said partial products, said parallel adders being operable for executing round-off addition at n respectively different bit positions (Al, A0), and said parallel adders generating n respective carry output signals which are outputted from said first circuit section as respective section carry output signals (C100, C101), said first circuit section further including data selector means controllable for selecting one out of n respective sets of bits constituting sum results produced from said n parallel adders of the first circuit section and for outputting the selected set of bits constituting one of the sum results (S3 to S0); a plurality of intermediate circuit sections (P2, P3, P4) coupled to receive respective pairs of intermediate numeral portions (A7 to A4, B7 to B4, . . . A18 to A13, B18 to B13) of said partial products, said pairs of intermediate numeral portions successively increasing in significance above said first portions, each intermediate circuit section of said plurality of intermediate circuit sections including a first parallel adder for adding together a pair of intermediate numeral portions supplied to said intermediate circuit section while fixedly adding a "1" state input carry thereto, and a second parallel adder for adding together the pair of numeral portions supplied to said intermediate circuit section while fixedly adding a "0" state input carry thereto, data selector means controllable for selecting one out of 2 respective sets of bits constituting sum results produced from said first and second parallel adders of said intermediate circuit section and for outputting the selected set of bits constituting said sum result (S7 to S4), carry selector means (120) operable for selecting one cut of n carry signals supplied from a preceding one of said circuit sections and for applying the selected carry signal to control said data selector means, and n section carry generating circuits each receiving respective carry output signals produced from said first and second parallel adders and a corresponding one of n carry output signals produced from a preceding one of said circuit sections, for generating n respective carry output signals; and a final circuit section coupled to receive respective most significant portions (A25 to A19, B25 to B19) of said partial products, including a first parallel adder for adding together said most significant portions while fixedly adding a "1" state input carry thereto, and a second parallel adder for adding together said most significant portions while fixedly adding a "0" state input carry thereto, data selector means controllable for selecting one out of 2 respective sets of bits constituting sum results produced from sadi first and second parallel adders of said final circuit section and for outputting the selected sum result (S25 to S19), carry selector means operable for selecting one out of n carry signals supplied from a preceding one of said circuit sections and for applying a selected carry signal to control said data selector means, and round-off position setting circuit means coupled to receive said n carry signals supplied from the preceding one of said circuit sections and to receive said most significant bits (S 1 25 , S 0 25 ) respectively produced from said first and second parallel adders of said final circuit section, and including logic circuit means responsive to a combination of logic states of said input carry signals (C112, C113) and most significant bits for producing corresponding output signals for controlling said respective data selector means and said carry selection means of said circuit sections, to thereby determine a position at which round-off processing has been executed, to thereby obtain an output result formed of the output bits (S25 to S0) produced from all of said data selector means.

Claim 6

A multiplier apparatus according to claim 3, and further comprising logic circuit means (703) responsive to a combination of states of respective most significant bits (701, 702) of said input numbers for producing an output signal (706) to be supplied to said round-off position setting circuit, and in which said round-off position setting circuit is responsive to a combination of logic states of said output signal (706), said input carry signals (C112, C113) and said most significant bits produced from said first and second parallel adders of said final circuit section for producing said output signals (S100) for controlling said respective data selector means and said selection means,

Claim 7

A multiplier apparatus according to claim 3, and further comprising logic circuit means (803) responsive to a combination of states cf respective most significant hits (801, 802) of said input numbers for producing output signals for selectively setting a round-off position of at least one of said parallel adders of said first circuit section (P1) to one of a plurality of respectively different bit positions in accordance with said combination of states, for thereby selectively establishing at least two respectively different sets of round-off positions in accordance with said combination of states.

Claim 8

A multiplier apparatus according to claim 3 wherein said first circuit section, said plurality of intermediate circuit sections and said final circuit section of said addition apparatus together operate, in combination, for executing a round-off process during an addition of two partial products, independently of additional circuitry for executing the round-off process.