US5018093A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High performance self-checking adder having small circuit area
Assignee: International Business Machines Corp
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Filing: 1990-01-02
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Granted: 1991-05-21
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Expires: 2010-01-02
Abstract
Abstract A carry select adder may be used in which carry inputs to ripple adder stages are not fixed. The adder stage determines which of the two ripple adders of that stage has output the correct sum while the variable carry input is equal to a given value. Then the variable carry input value is switched to a different value and the adder stage determines the correct output sum from the other ripple adder. The adder performs self-checking by comparing these two sums to ensure that the output sum is accurate.
Inventors
- 👤 Feng-Hsien W. Shih
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1497; G06F11/16; G06F11/1608; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
124 words
A circuit for checking for faults in an adder stage having a first ripple adder and a second ripple adder said first ripple adder having a variable carry input and said second ripple adder having a carry input opposite that of said first adder, said checking circuit comprising: means for selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; first means for storing said selected output when said variable carry input is equal to a first value; second means for storing said selected output when said variable carry input is equal to a second value; and means for providing an error signal in response to said stored outputs.
Claim 2
Dependent Claim
124 words
A circuit for checking for faults in an adder stage having a first ripple adder and a second ripple adder said first ripple adder having a variable carry input and said second ripple adder having a carry input opposite that of said first adder, said checking circuit comprising: means for selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; first means for storing said selected output when said variable carry input is equal to a first value; second means for storing said selected output when said variable carry input is equal to a second value; and means for providing an error signal in response to said stored outputs.
Claim 3
Dependent Claim
16 words
A circuit as claimed in claim 1, wherein said error signal providing means comprises a comparator.
Claim 4
Dependent Claim
58 words
A circuit as claimed in claim 1, wherein said carry output from said previous stage is determined by a first carry propagation select circuit which is responsive to carry outputs from first and second ripple adders of said previous stage, to a carry output from a stage prior to said previous stage, and to said variable carry input.
Claim 5
Dependent Claim
53 words
A circuit as claimed in claim 3, wherein said adder stage in which faults are checked further comprises: a second carry propagation select circuit connected in parallel with said first carry propagation select circuit; and means for providing a second error signal in response to said first and second carry propagation select circuits.
Claim 6
Dependent Claim
17 words
A circuit as claimed in claim 4, wherein said second error signal providing means comprises a comparator.
Claim 7
Dependent Claim
32 words
A circuit as claimed in claim 1, wherein said selected output stored in said first storing means is provided as sum output bits of said adder stage in which faults are checked.
Claim 8
Dependent Claim
119 words
A self-checking adder having a plurality of stages, at least one of said stages comprising: a first ripple adder having a variable carry input; a second ripple adder having a carry input which is the inverse of said variable carry input; means for selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; and means for providing a first error signal in response to an output selected by said selecting means when said variable carry input is equal to a first value and in response to an output selected by said selecting means when said variable carry input is equal to a second value.
Claim 9
Dependent Claim
119 words
A self-checking adder having a plurality of stages, at least one of said stages comprising: a first ripple adder having a variable carry input; a second ripple adder having a carry input which is the inverse of said variable carry input; means for selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; and means for providing a first error signal in response to an output selected by said selecting means when said variable carry input is equal to a first value and in response to an output selected by said selecting means when said variable carry input is equal to a second value.
Claim 10
Dependent Claim
19 words
A self-checking adder as claimed in claim 7, wherein said plurality of stages have a varying number of bits.
Claim 11
Dependent Claim
18 words
A self-checking adder as claimed in claim 7, wherein said first error signal providing means comprises a comparator.
Claim 12
Dependent Claim
41 words
A self-checking adder as claimed in claim 7, wherein a first of said stages comprises: a third ripple adder; a fourth ripple adder; and means for providing an error signal in response to outputs of said third and fourth ripple adders.
Claim 13
Dependent Claim
59 words
A self-checking adder as claimed in claim 7, wherein said carry output from said previous stage is determined by a first carry propagation select circuit which is responsive to carry outputs from first and second ripple adders of said previous stage, to a carry output from a stage prior to said previous stage, and to said variable carry input.
Claim 14
Dependent Claim
51 words
A self-checking adder as claimed in claim 11, wherein said at least one stage further comprises: a second carry propagation select circuit connected in parallel with said first carry propagation select circuit; and means for providing a second error signal in response to said first and second carry propagation select circuits.
Claim 15
Dependent Claim
18 words
A self-checking adder as claimed in claim 12, wherein said second error signal providing means comprises a comparator.
Claim 16
Dependent Claim
41 words
A self-checking adder as claimed in claim 7, wherein said output selected by said selecting means when said variable carry input is equal to said first value is used as a portion of sum output bits output by said self-checking adder.
Claim 17
Independent Claim
118 words
A method for checking for faults in a stage of a self-checking adder, said stage including a first ripple adder and a second ripple adder, said method comprising the steps of: (a) providing a variable carry input to said first ripple adder; (b) providing a carry input to said second ripple adder which is the inverse of said variable carry input; (c) selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; (d) inverting said variable carry input; (e) repeating steps (a) through (c) with said variable carry input inverted; and (f) providing a first error signal in response to said selected outputs.
Claim 18
Independent Claim
118 words
A method for checking for faults in a stage of a self-checking adder, said stage including a first ripple adder and a second ripple adder, said method comprising the steps of: (a) providing a variable carry input to said first ripple adder; (b) providing a carry input to said second ripple adder which is the inverse of said variable carry input; (c) selecting an output of one of said ripple adders in response to said variable carry input and to a carry output from a previous stage; (d) inverting said variable carry input; (e) repeating steps (a) through (c) with said variable carry input inverted; and (f) providing a first error signal in response to said selected outputs.
Claim 19
Dependent Claim
52 words
The method claimed in claim 15, further comprising the step of determining said carry output from said previous stage in response to carry outputs from first and second ripple adders of said previous stage, to a carry output from a stage prior to said previous stage, and to said variable carry input.
Claim 20
Dependent Claim
29 words
The method claimed in claim 15, further comprising the step of providing one of said selected outputs as sum output bits output by said stage being checked for faults.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-20 | 1994-11-19 | 1995-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-20 | 1998-11-19 | 1999-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-20 | 2002-11-19 | 2003-05-21 | $7700.00 | Window Closed / Lapsed |