Abstract A process for making vertical electrical interconnections in a variety of integrated circuits and novel IC structures produced thereby wherein buried conductors are provided within a dielectric layer located above a silicon substrate having active or passive devices formed therein. Internal edges of only one or selected ones of the conductors are provided with an insulating coating, so that an adjacent via may be filled with a conductive material and still be electrically isolated from the one conductor or conductors. One or more vias are etched directly through the other buried conductor or conductors and also filled with a conductive material which electrically connects this buried conductor or conductors to both the substrate and to an upper level of metallization, and alternatively to intermediate conductors or other components. In this manner, lateral offset spacing requirements for masking and etching is minimized to thereby maximize the achievable component packing density within the IC structure being manufactured.
A process for manufacturing multi-level conductor type integrated circuits which includes the steps of: a. providing a semiconductor substrate having active or passive devices therein to which electrical connections must be made, b. forming a dielectric layer on said substrate having certain strips of conductor therein which must be connected to said devices and certain strips of conductor therein which must be maintained electrically isolated from said devices, c. opening first vias in said dielectric layer above conductive strips to be electrically isolated and exposing edges of said conductive strips, d. insulating said edges of said strips exposed by said vias, e. continuing to etch said first vias on through to reach said semiconductor substrate, while also f. opening second vias through said conductive strips which are to be connected to said substrate, and then g. forming vertical electrical interconnects in said first and second vias whereby said active and passive devices in said semiconductor substrate may be both electrically connected to and isolated from said conductive strips within said dielectric layer and may be further interconnected to a surface layer of conductor on the surface of said dielectric layer.
Claim 2
Dependent Claim
190 words
A process for manufacturing multi-level conductor type integrated circuits which includes the steps of: a. providing a semiconductor substrate having active or passive devices therein to which electrical connections must be made, b. forming a dielectric layer on said substrate having certain strips of conductor therein which must be connected to said devices and certain strips of conductor therein which must be maintained electrically isolated from said devices, c. opening first vias in said dielectric layer above conductive strips to be electrically isolated and exposing edges of said conductive strips, d. insulating said edges of said strips exposed by said vias, e. continuing to etch said first vias on through to reach said semiconductor substrate, while also f. opening second vias through said conductive strips which are to be connected to said substrate, and then g. forming vertical electrical interconnects in said first and second vias whereby said active and passive devices in said semiconductor substrate may be both electrically connected to and isolated from said conductive strips within said dielectric layer and may be further interconnected to a surface layer of conductor on the surface of said dielectric layer.
Claim 3
Dependent Claim
24 words
The process defined in claim 1 wherein said conductive strips are polysilicon which are insulated by the formation of a silicon dioxide coating thereon.
Claim 4
Dependent Claim
51 words
The process defined in claim 2 wherein said vertical electrical interconnects are formed within said first and second vias by first coating said vias with a layer of materials selected from the group consisting of titanium or titanium alloys, titanium nitride, and refractory metals and then coating said layer with tungsten.