Method of fabricating semiconductor device

Claim 1

A method of fabricating a semiconductor device including an NPN transistor and a PNP transistor, comprising the steps of: forming a well region in a predetermined region in a semiconductor substrate of a first conduction type, the well region being of a second conduction type; forming a base diffusion layer of the first conduction type in the well region; forming a base diffusion layer of the second conduction type in a predetermined region in the semiconductor substrate; forming a first polycrystalline silicon film (115) on the semiconductor substrate; introducing impurity corresponding to a first conduction type into a portion of the first polycrystalline silicon film (115) which extends above an NPN-transistor-forming region; introducing impurity corresponding to a second conduction type into a portion of the first polycrystalline silicon film (115) which extends above a PNP-transistor-forming region; forming a first insulating film (7) on the first polycrystalline silicon film; etching the first insulating film and the first polycrystalline silicon film, and simultaneously forming emitter lead-out electrodes (9, 117) and collector lead-out electrodes (10, 118) in regions above emitter-contact-forming regions and collector-contact-forming regions of the NPN transistor and the PNP transistor; forming second insulating films (11, 12) at sides of the emitter and collector lead-out electrodes; simultaneously forming base contacts (101, 104) of the NPN transistor and the PNP transistor; forming a second polycrystalline silicon film (119) on the semiconductor substrate; introducing impurity corresponding to the second conduction type into a portion of the second polycrystalline silicon film (119) which extends above the NPN-transistor-forming region; introducing impurity corresponding to the first conduction type into a portion of the second polycrystalline silicon film (119) which extends above the PNP-transistor-forming region; etching the second polycrystalline silicon film to form a base lead-out electrode (13) of the NPN transistor and a base lead-out electrode (120) of the PNP transistor, wherein the base lead-out electrode of the NPN transistor includes impurity corresponding to the second conduction type, and wherein the base lead-out electrode of the PNP transistor includes impurity corresponding to the first conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form emitter diffusion layers (15, 121), collector contact diffusion layers (17, 123), and base contact diffusion layers (16, 122) of the NPN transistor and the PNP transistor; locating an end of the emitter diffusion layer (15, 121) and a first end of the base contact diffusion layer (16, 122) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the emitter lead-out electrode (9, 117) in each of the NPN transistor and the PNP transistor; and locating a second end of the base contact diffusion layer (16, 122) and an end of the collector contact diffusion layer (17, 123) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the collector lead-out electrode (10, 118) in each of the NPN transistor and the PNP transistor.

Claim 2

A method of fabricating a semiconductor device including an NPN transistor and a PNP transistor, comprising the steps of: forming a well region in a predetermined region in a semiconductor substrate of a first conduction type, the well region being of a second conduction type; forming a base diffusion layer of the first conduction type in the well region; forming a base diffusion layer of the second conduction type in a predetermined region in the semiconductor substrate; forming a first polycrystalline silicon film (115) on the semiconductor substrate; introducing impurity corresponding to a first conduction type into a portion of the first polycrystalline silicon film (115) which extends above an NPN-transistor-forming region; introducing impurity corresponding to a second conduction type into a portion of the first polycrystalline silicon film (115) which extends above a PNP-transistor-forming region; forming a first insulating film (7) on the first polycrystalline silicon film; etching the first insulating film and the first polycrystalline silicon film, and simultaneously forming emitter lead-out electrodes (9, 117) and collector lead-out electrodes (10, 118) in regions above emitter-contact-forming regions and collector-contact-forming regions of the NPN transistor and the PNP transistor; forming second insulating films (11, 12) at sides of the emitter and collector lead-out electrodes; simultaneously forming base contacts (101, 104) of the NPN transistor and the PNP transistor; forming a second polycrystalline silicon film (119) on the semiconductor substrate; introducing impurity corresponding to the second conduction type into a portion of the second polycrystalline silicon film (119) which extends above the NPN-transistor-forming region; introducing impurity corresponding to the first conduction type into a portion of the second polycrystalline silicon film (119) which extends above the PNP-transistor-forming region; etching the second polycrystalline silicon film to form a base lead-out electrode (13) of the NPN transistor and a base lead-out electrode (120) of the PNP transistor, wherein the base lead-out electrode of the NPN transistor includes impurity corresponding to the second conduction type, and wherein the base lead-out electrode of the PNP transistor includes impurity corresponding to the first conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form emitter diffusion layers (15, 121), collector contact diffusion layers (17, 123), and base contact diffusion layers (16, 122) of the NPN transistor and the PNP transistor; locating an end of the emitter diffusion layer (15, 121) and a first end of the base contact diffusion layer (16, 122) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the emitter lead-out electrode (9, 117) in each of the NPN transistor and the PNP transistor; and locating a second end of the base contact diffusion layer (16, 122) and an end of the collector contact diffusion layer (17, 123) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the collector lead-out electrode (10, 118) in each of the NPN transistor and the PNP transistor.

Claim 7

A method of fabricating a semiconductor device including an NPN transistor and a PNP transistor, comprising the steps of: forming a well region in a predetermined region in a semiconductor substrate of a first conduction type, the well region being of a second conduction type; forming a base diffusion layer of the first conduction type in the well region; forming a base diffusion layer of the second conduction type in a predetermined region in the semiconductor substrate; forming a first polycrystalline silicon film (115) on the semiconductor substrate, the first polycrystalline silicon film (115) including impurity corresponding to the first conduction type; forming a first insulating film (7) on the first polycrystalline silicon film; etching the first insulating film (7) and the first polycrystalline silicon film (115) to form a base lead-out electrode (120) in a region above a base-contact-forming region of the PNP transistor, and to form an emitter lead-out electrode (9) and a collector lead-out electrode (10) in regions above an emitter-contact-forming region and a collector-contact-forming region of the NPN transistor; forming second insulating films (11, 12) at sides of the base lead-out electrode (120) of the PNP transistor, and the emitter and collector lead-out electrodes (9, 10) of the NPN transistor; simultaneously forming a base contact (101) of the NPN transistor, and an emitter contact (103) and a collector contact (105) of the PNP transistor; forming a second polycrystalline silicon film (119) on the semiconductor substrate; introducing impurity corresponding to the second conduction type into the second polycrystalline silicon film (119); etching the second polycrystalline silicon film to simultaneously form a base lead-out electrode (13) of the NPN transistor, and an emitter lead-out electrode (117) and a collector lead-out electrode (118) of the PNP transistor, wherein the base lead-out electrode (13) of the NPN transistor, and the emitter lead-out electrode (117) and the collector lead-out electrode (118) of the PNP transistor include impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrodes, the collector lead-out electrodes, and the base lead-out electrodes of the NPN transistor and the PNP transistor to form emitter diffusion layers (15, 121), collector contact diffusion layers (17, 123), and base contact diffusion layers (16, 122) of the NPN transistor and the PNP transistor; locating an end of the emitter diffusion layer (15, 121) and a first end of the base contact diffusion layer (16, 122) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the emitter lead-out electrode (9, 117) in each of the NPN transistor and the PNP transistor; and locating a second end of the base contact diffusion layer (16, 122) and an end of the collector contact diffusion layer (17, 123) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the collector lead-out electrode (10, 118) in each of the NPN transistor and the PNP transistor.

Claim 8

A method of fabricating a semiconductor device including an NPN transistor and a PNP transistor, comprising the steps of: forming a well region in a predetermined region in a semiconductor substrate of a first conduction type, the well region being of a second conduction type; forming a base diffusion layer of the first conduction type in the well region; forming a base diffusion layer of the second conduction type in a predetermined region in the semiconductor substrate; forming a first polycrystalline silicon film (115) on the semiconductor substrate, the first polycrystalline silicon film (115) including impurity corresponding to the first conduction type; forming a first insulating film (7) on the first polycrystalline silicon film; etching the first insulating film (7) and the first polycrystalline silicon film (115) to form a base lead-out electrode (120) in a region above a base-contact-forming region of the PNP transistor, and to form an emitter lead-out electrode (9) and a collector lead-out electrode (10) in regions above an emitter-contact-forming region and a collector-contact-forming region of the NPN transistor; forming second insulating films (11, 12) at sides of the base lead-out electrode (120) of the PNP transistor, and the emitter and collector lead-out electrodes (9, 10) of the NPN transistor; simultaneously forming a base contact (101) of the NPN transistor, and an emitter contact (103) and a collector contact (105) of the PNP transistor; forming a second polycrystalline silicon film (119) on the semiconductor substrate; introducing impurity corresponding to the second conduction type into the second polycrystalline silicon film (119); etching the second polycrystalline silicon film to simultaneously form a base lead-out electrode (13) of the NPN transistor, and an emitter lead-out electrode (117) and a collector lead-out electrode (118) of the PNP transistor, wherein the base lead-out electrode (13) of the NPN transistor, and the emitter lead-out electrode (117) and the collector lead-out electrode (118) of the PNP transistor include impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrodes, the collector lead-out electrodes, and the base lead-out electrodes of the NPN transistor and the PNP transistor to form emitter diffusion layers (15, 121), collector contact diffusion layers (17, 123), and base contact diffusion layers (16, 122) of the NPN transistor and the PNP transistor; locating an end of the emitter diffusion layer (15, 121) and a first end of the base contact diffusion layer (16, 122) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the emitter lead-out electrode (9, 117) in each of the NPN transistor and the PNP transistor; and locating a second end of the base contact diffusion layer (16, 122) and an end of the collector contact diffusion layer (17, 123) at positions directly below a portion of the second insulating films (11, 12) which extends at a side of the collector lead-out electrode (10, 118) in each of the NPN transistor and the PNP transistor.