System for selecting next instruction address between unit incremented address and address from table specified by operating condition signals

Claim 2

A microprogram branching method comprising the steps of: generating a next microinstruction address by successively incrementing an address of current microinstruction; generating a branched next microinstruction address from a branch address table based on predetermined operating condition signals, said branch address table prestoring a plurality of branch addresses in correspondence with operating condition signals; discriminating whether or not a branch is to be made depending on the predetermined operating condition signals and obtaining a discrimination result; selecting the next microinstruction address normally and selecting the branched next microinstruction address when the discrimination result indicates that the branch is to be made; and outputting data from an address location of a main memory depending on the selected address, said main memory prestoring microprograms.

Claim 3

The microprogram branching method as claimed in claim 1 wherein said selecting step designates the data which is to be read out from the main memory based on the selected address and said output step outputs said data based on the discrimination result when said discriminating step discriminates certain branch conditions.

Claim 4

The microprogram branching method as claimed in claim 2 wherein said selecting step selects the data from the main memory based on said selected address and said output step outputs said data when a branch, which is presently processed, is an unconditional branch.

Claim 5

The microprogram branching method as claimed in claim 1 wherein said latter generating step and said discriminating step respectively use a programmable logic array.

Claim 6

The microprogram branching method as claimed in claim 1 which is employed in a microsequencer which controls each part of a direct memory access controller by the microprograms.

Claim 7

A microsequencer adaptable to control each part of a direct memory access controller, said microsequencer comprising: memory means for prestoring microprograms; first generating means for generating a next microinstruction address by successively incrementing an address of current microinstruction; a branch address table prestored with a plurality of branch addresses in correspondence with operating condition signals; second generating means for generating a branched next microinstruction address from said branch address table based on predetermined operating condition signals; discriminating means for discriminating whether or not a branch is to be made based on the predetermined operating condition signals and for obtaining a discrimination result; selecting means for selecting the next microinstruction address normally and selecting the branched next microinstruction address when the discrimination result indicates that the branch is to be made; and output means for outputting data which is read out from an address location of said memory means based on the address selected by said selecting means wherein, said second generating means generating said branched next microinstruction address prior to said selecting means selecting an address based on the discriminating result.

Claim 8

A microsequencer adaptable to control each part of a direct memory access controller, said microsequencer comprising: memory means for prestoring microprograms; first generating means for generating a next microinstruction address by successively incrementing an address of current microinstruction; a branch address table prestored with a plurality of branch addresses in correspondence with operating condition signals; second generating means for generating a branched next microinstruction address from said branch address table based on predetermined operating condition signals; discriminating means for discriminating whether or not a branch is to be made based on the predetermined operating condition signals and for obtaining a discrimination result; selecting means for selecting the next microinstruction address normally and selecting the branched next microinstruction address when the discrimination result indicates that the branch is to be made; and output means for outputting data which is read out from an address location of said memory means based on the address selected by said selecting means wherein, said second generating means generating said branched next microinstruction address prior to said selecting means selecting an address based on the discriminating result.

Claim 9

The microsequencer as claimed in claim 6 wherein said selecting means selects the data from said memory means based on said selected address and said output means outputs said data via said output means based on the discrimination result when said discriminating means discriminates certain branch conditions.

Claim 10

The microsequencer as claimed in claim 7 wherein said selecting means selects the data from said memory means based on said selected address and said output means outputs said data via said output means when a branch which is presently processed is an unconditional branch.

Claim 11

The microsequencer as claimed in claim 6 wherein said second generating means and said discriminating means are respectively made up of a programmable logic array.

Claim 12

The microsequencer as claimed in claim 6 wherein said memory means comprises a read only memory.

Claim 13

The microsequencer as claimed in claim 6 wherein said memory means comprises a read only memory and said output means comprises a register for storing an output data of said read only memory.