US5202625A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of testing interconnections in digital systems by the use of bidirectional drivers
Assignee: Raytheon Co
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Filing: 1991-07-03
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Granted: 1993-04-13
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Expires: 2011-07-03
Abstract
Abstract A bidirectional boundary scan circuit cell for use in boundary scan testing of device interconnections including a scan flip-flop, a first multiplexer responsive to the scan flip-flop and to a device output if the associated pin is for an output function for controllably providing as its output a replica of the scan register output or the device output, a three-state buffer responsive to the output of the first multiplexer and having its output connected to the associated device I/O pin, an input buffer whose input is connected to the associated device input/output pin and whose output comprises an input to the device if the associated I/O pin provides an input function, and a second multiplexer responsive the input buffer and a serial scan input for controllably providing as the input to the scan flip-flop a replica of the output of the input buffer or a replica of the serial scan input. For scan test purposes, the scan cell is configurable as a transmit cell for driving the associated I/O pin or as a receiver for storing the signal at the associated I/O pin.
Inventors
- 👤 William D. Farwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:01
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318544; G01R31/31855; G01R31/318572; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/221
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A boundary scan circuit cell for use in a scan chain in a device having a plurality of input/output pins wherein each scan cell is associated with a specific input/output pin, the boundary scan cell circuit comprising: a scan flip-flop; a three-state output buffer responsive to the output of said scan flip-flop and having its output connected to the associated device input/output pin; an input buffer whose input is connected to the associated device input/output pin; and multiplexer responsive to said input buffer and a serial scan input for controllably providing as the input to said scan flip-flop; wherein for scan test purposes the scan cell is configurable for driving the signal on the associated I/O pin in accordance with the scan input stored in said scan flip-flop, and is capable of storing in said scan flip-flop the signal observed on its associated I/O pin, the observed signal being provided by said output buffer or by a three stage output buffer of the scan cell of an interconnected I/O pin.
Claim 2
Dependent Claim
170 words
A boundary scan circuit cell for use in a scan chain in a device having a plurality of input/output pins wherein each scan cell is associated with a specific input/output pin, the boundary scan cell circuit comprising: a scan flip-flop; a three-state output buffer responsive to the output of said scan flip-flop and having its output connected to the associated device input/output pin; an input buffer whose input is connected to the associated device input/output pin; and multiplexer responsive to said input buffer and a serial scan input for controllably providing as the input to said scan flip-flop; wherein for scan test purposes the scan cell is configurable for driving the signal on the associated I/O pin in accordance with the scan input stored in said scan flip-flop, and is capable of storing in said scan flip-flop the signal observed on its associated I/O pin, the observed signal being provided by said output buffer or by a three stage output buffer of the scan cell of an interconnected I/O pin.
Claim 3
Dependent Claim
173 words
A boundary scan circuit cell for use in a scan chain in a device having a plurality of input/output (I/O) pins wherein each scan cell is associated with a specific I/O pin, the boundary scan cell circuit comprising: input buffering means responsive to signals applied to the associated I/O pin for providing a buffered input signal; multiplexer for controllably outputting said buffered input signal or a scan input signal; a scan flip-flop for storing the output of said multiplexer; and output buffering means responsive to said scan flip-flop for driving the associated device I/O pin; wherein for scan test purposes the scan cell is configurable for driving the signal on the associated I/O pin in accordance with the scan input stored in said scan flip-flop, and is capable of storing in said flip-flop the signal observed on its associated I/O pin, where the observed signal is provided either by said output buffering means or by the output buffering means of the scan cell of another device which is interconnected to the I/O pin.
Claim 4
Dependent Claim
173 words
A boundary scan circuit cell for use in a scan chain in a device having a plurality of input/output (I/O) pins wherein each scan cell is associated with a specific I/O pin, the boundary scan cell circuit comprising: input buffering means responsive to signals applied to the associated I/O pin for providing a buffered input signal; multiplexer for controllably outputting said buffered input signal or a scan input signal; a scan flip-flop for storing the output of said multiplexer; and output buffering means responsive to said scan flip-flop for driving the associated device I/O pin; wherein for scan test purposes the scan cell is configurable for driving the signal on the associated I/O pin in accordance with the scan input stored in said scan flip-flop, and is capable of storing in said flip-flop the signal observed on its associated I/O pin, where the observed signal is provided either by said output buffering means or by the output buffering means of the scan cell of another device which is interconnected to the I/O pin.
Claim 5
Dependent Claim
14 words
The scan cell of claim 2 wherein said flip-flop is a storage means flip-flop.
Claim 6
Dependent Claim
15 words
The scan cell of claim 2 wherein said output buffering means comprises a three-state buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-12 | 1996-10-12 | 1997-04-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-12 | 2000-10-12 | 2001-04-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-12 | 2004-10-12 | 2005-04-13 | $7700.00 | Window Closed / Lapsed |