EP0425416A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A self testable boundary logic circuit
Assignee: International Business Machines Corp
•
Filing: 1990-09-21
•
Granted: —
•
Expires: 2010-09-21
Abstract
Abstract The present invention implements self testable boundary logic by using a tristate pass gate (60)and a tristate receiver (70)in combination with a linear feedback shift register (30), a storage register (120), and level sensitive scan design (LSSD) techniques. The linear feedback shift register (LFSR) shifts data into a storage register which is connected to the data inputs of the boundary logic through the tristate pass gate. The outputs of the tristate input receiver are also connected to the inputs of the boundary logic so that the boundary logic can receive data from both the data input of the integrated circuit (data path) or from the storage register connected to the LFSR. The tristate pass gate and receiver are enabled through a self test signal such that when the pass gate is enabled the receiver is not enabled and vice versa. In this way the boundary logic can only get data from either the storage register or through the receiver but not both. In this configuration data from the storage register can be input into the boundary logic without going through a multiplexer in the data path and incurring the associated delay. The boundary logic can then be self tested using ordinary LSSD techniques. This self testing can also be performed with a minimum of additional silicon area being used for the self test structures.
Inventors
- 👤 Anthony Correale Jr.
- 👤 Richard Michael Doney
- 👤 Kim Edward O'donnell
- 👤 Andrew Kegl
- 👤 Erwin Arthur Tate
- 👤 David M. Wu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 16:11
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318572
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
287 words
A self testable boundary logic circuit comprising a linear feedback shift register, a multiple input shift register, a tristate receiver, a tristate pass gate, input boundary logic, internal logic, and a self test signal; said circuit being characterized in that : said internal logic is connected to said linear feedback shift register and receives test pattern scan information from said linear feedback shift register, said multiple input shift register is connected to said internal logic and receives scan information from said internal logic, said internal logic has data outputs connected to inputs of said tristate pass gate, said tristate pass gate receiving test data from said internal logic, said internal logic is connected to said input boundary logic and receives data from said input boudary logic, said tristate receiver and said tristate pass gate have outputs being connected to said input boundary logic, said tristate receiver has outputs being enabled in response to said self test signal being in a first state, said tristate receiver having outputs set to a high impedance state in response to said self test signal being in a second state, said tristate pass gate has outputs being enabled in response to said self test signal being in said second state, said tristate pass gate having outputs set to a high impedance state in response to said self test signal in said first state, said input boundary logic receives test pattern scan information from said linear feedback shift register through said internal logic and said tristate pass gate in response to said self test signal being in said second state, and said input boundary logic receives data from said tristate receiver in response to said self test signal being in said first state.
Claim 2
Dependent Claim
287 words
A self testable boundary logic circuit comprising a linear feedback shift register, a multiple input shift register, a tristate receiver, a tristate pass gate, input boundary logic, internal logic, and a self test signal; said circuit being characterized in that : said internal logic is connected to said linear feedback shift register and receives test pattern scan information from said linear feedback shift register, said multiple input shift register is connected to said internal logic and receives scan information from said internal logic, said internal logic has data outputs connected to inputs of said tristate pass gate, said tristate pass gate receiving test data from said internal logic, said internal logic is connected to said input boundary logic and receives data from said input boudary logic, said tristate receiver and said tristate pass gate have outputs being connected to said input boundary logic, said tristate receiver has outputs being enabled in response to said self test signal being in a first state, said tristate receiver having outputs set to a high impedance state in response to said self test signal being in a second state, said tristate pass gate has outputs being enabled in response to said self test signal being in said second state, said tristate pass gate having outputs set to a high impedance state in response to said self test signal in said first state, said input boundary logic receives test pattern scan information from said linear feedback shift register through said internal logic and said tristate pass gate in response to said self test signal being in said second state, and said input boundary logic receives data from said tristate receiver in response to said self test signal being in said first state.
Claim 3
Dependent Claim
118 words
The circuit as in claim 1, further comprising output boundary logic, a storage register, and an off chip driver, with : said internal logic being connected to said output boundary logic and transmitting data to said output boundary logic, said output boundary logic being connected to said storage register and said off chip driver, said storage register being connected to said multiple input storage register, said output boundary logic transmitting scan information to said multiple input shift register through said storage register in response to said self test signal being in said second state, and said output boundary logic transmitting data to said off chip driver in response to said self test signal being in said first state.
Claim 4
Independent Claim
149 words
A method of testing self testable logic circuits comprising: generating test pattern scan information in a linear feedback shift register, applying said test pattern scan information to internal logic, and input boundary logic, prohibiting said test pattern scan information from application to said input boundary logic in response to said self test signal being in the first state, said prohibition providing no transmission delay between a receiver and said input boundary logic, said test pattern scan information being applied to said input boundary logic through a tristate pass gate and a first storage register in response to a self test signal being in a second state, sampling scan information from said internal logic and said input boundary logic, said sampled scan information being stored in a multiple input shift register, comparing said sampled test data with signature test data results to determine said self testable logic circuit functional performance.
Claim 5
Independent Claim
149 words
A method of testing self testable logic circuits comprising: generating test pattern scan information in a linear feedback shift register, applying said test pattern scan information to internal logic, and input boundary logic, prohibiting said test pattern scan information from application to said input boundary logic in response to said self test signal being in the first state, said prohibition providing no transmission delay between a receiver and said input boundary logic, said test pattern scan information being applied to said input boundary logic through a tristate pass gate and a first storage register in response to a self test signal being in a second state, sampling scan information from said internal logic and said input boundary logic, said sampled scan information being stored in a multiple input shift register, comparing said sampled test data with signature test data results to determine said self testable logic circuit functional performance.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.