Low power level converter

Claim 2

A low power level converter comprising: a first transistor having a first current electrode coupled to a first power supply voltage terminal, a control electrode for receiving a control signal, and a second current electrode; a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving a first input signal, and a second current electrode; a third transistor having a first current electrode coupled to said second current electrode of said second transistor, a control electrode coupled to said second current electrode of said second transistor, and a second current electrode coupled to a second power supply voltage terminal; a fourth transistor having a first current electrode coupled to said first current electrode of said third transistor, a control electrode coupled to said control electrode of said first transistor for receiving said control signal, and a second current electrode; a fifth transistor having a first current electrode coupled to said second current electrode of said fourth transistor, a control electrode coupled to said second current electrode of said second transistor, and a second current electrode coupled to said second power supply voltage terminal; and a sixth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving a second input signal, and a second current electrode coupled to said first current electrode of said fifth transistor and for providing an output signal.

Claim 3

The low power level converter of claim 1 wherein said control signal is characterized as being a CMOS level signal.

Claim 4

The low power level converter of claim 1 wherein at least one of said first, second and sixth transistors are enhancement-mode P-channel MOSFET transistors and at least one of said third, fourth and fifth transistors are enhancement-mode N-channel MOSFET transistors.

Claim 5

The low power level converter of claim 1 wherein at least one of said first, second and sixth transistors are P-channel CMOS transistors and at least one of said third, fourth and fifth transistors are N-channel CMOS transistors.

Claim 6

A lower power ECL-to-CMOS level converter for receiving an ECL level input signal and providing an output signal at CMOS logic levels, comprising: means for receiving an ECL level signal and providing a first voltage and a second voltage of a predetermined logic level in response thereto; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate for receiving a control signal characterized as being a CMOS-level signal, and a drain; a second P-channel transistor having a source coupled to said drain of first P-channel transistor, a gate for receiving said first voltage, and a drain; a first N-channel transistor having a drain coupled to said drain of said second P-channel transistor, a source coupled to a second power supply voltage terminal, and a gate coupled to said drain of said first N-channel transistor; a second N-channel transistor having a first source/drain terminal coupled to said drain of said second P-channel transistor, a gate coupled to said gate of said first P channel transistor, and a second source/drain terminal; a third N-channel transistor having a source coupled to said second power supply voltage terminal, a gate coupled to said gate of said first N-channel transistor, and a drain coupled to said second source/drain terminal of said second N-channel transistor; and a third P-channel transistor having a source coupled to said first power supply voltage terminal, a drain coupled to said drain of said third N-channel transistor and providing a CMOS level output signal thereon, and a gate for receiving said second voltage.

Claim 7

A lower power ECL-to-CMOS level converter for receiving an ECL level input signal and providing an output signal at CMOS logic levels, comprising: means for receiving an ECL level signal and providing a first voltage and a second voltage of a predetermined logic level in response thereto; a first P-channel transistor having a source coupled to a first power supply voltage terminal, a gate for receiving a control signal characterized as being a CMOS-level signal, and a drain; a second P-channel transistor having a source coupled to said drain of first P-channel transistor, a gate for receiving said first voltage, and a drain; a first N-channel transistor having a drain coupled to said drain of said second P-channel transistor, a source coupled to a second power supply voltage terminal, and a gate coupled to said drain of said first N-channel transistor; a second N-channel transistor having a first source/drain terminal coupled to said drain of said second P-channel transistor, a gate coupled to said gate of said first P channel transistor, and a second source/drain terminal; a third N-channel transistor having a source coupled to said second power supply voltage terminal, a gate coupled to said gate of said first N-channel transistor, and a drain coupled to said second source/drain terminal of said second N-channel transistor; and a third P-channel transistor having a source coupled to said first power supply voltage terminal, a drain coupled to said drain of said third N-channel transistor and providing a CMOS level output signal thereon, and a gate for receiving said second voltage.

Claim 8

The low power ECL-to-CMOS level converter of claim 5 further comprising BICMOS output driver means, coupled to said drain of said third P-channel transistor, for providing a second output signal in response to said CMOS-level output signal.

Claim 9

The low power ECL-to-CMOS level converter of claim 6 further comprising feedback means, for providing said control signal in response to said second output signal.

Claim 10

The low power ECL-to-CMOS level converter of claim 5 further comprising feedback means, for providing said control signal in response to a complement of said output signal.

Claim 11

The low power ECL-to-CMOS level converter of claim 5 wherein at least one of said P-channel transistors are enhancement-mode P-channel MOSFET transistors and at least one of said N-channel transistors are enhancement-mode N-channel MOSFET transistors.

Claim 12

A low power ECL-to-CMOS level converter for receiving an ECL level input signal and providing an output signal at CMOS levels, comprising: input means for receiving an ECL-level signal and providing first and second input voltages, said second input voltage reversed in phase relative to said first input voltage; first and second power supply voltage terminals for supplying first and second operating voltages; a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate for receiving a control signal characterized as being a CMOS-level signal, and a drain; a second P-channel transistor having a source coupled to said drain of first P-channel transistor, a gate for receiving said first input voltage, and a drain; a first N-channel transistor having a drain coupled to said drain of said second P-channel transistor, a source coupled to said second power supply voltage terminal, and a gate coupled to said drain of said first N-channel transistor; a second N-channel transistor having a first source/drain terminal coupled to said drain of said first N-channel transistor, a gate coupled to said gate of said first P-channel transistor, and a second source/drain terminal; a third N-channel transistor having a source coupled to said second power supply voltage terminal, a gate coupled to said drain of said first N-channel transistor, and a drain coupled to said second source/drain terminal of said second N-channel transistor; a third P-channel transistor having a source coupled to said first power supply voltage terminal, a drain coupled to said drain of said third N-channel transistor and providing a CMOS-level output voltage thereon, and a gate for receiving said second input voltage; and BICMOS output driver means, coupled to said drain of said third P-channel transistor for providing an output signal of said ECL-to-CMOS level converter in response to a complement of said CMOS-level signal and for providing said output signal as said control signal.

Claim 13

A low power ECL-to-CMOS level converter for receiving an ECL level input signal and providing an output signal at CMOS levels, comprising: input means for receiving an ECL-level signal and providing first and second input voltages, said second input voltage reversed in phase relative to said first input voltage; first and second power supply voltage terminals for supplying first and second operating voltages; a first P-channel transistor having a source coupled to said first power supply voltage terminal, a gate for receiving a control signal characterized as being a CMOS-level signal, and a drain; a second P-channel transistor having a source coupled to said drain of first P-channel transistor, a gate for receiving said first input voltage, and a drain; a first N-channel transistor having a drain coupled to said drain of said second P-channel transistor, a source coupled to said second power supply voltage terminal, and a gate coupled to said drain of said first N-channel transistor; a second N-channel transistor having a first source/drain terminal coupled to said drain of said first N-channel transistor, a gate coupled to said gate of said first P-channel transistor, and a second source/drain terminal; a third N-channel transistor having a source coupled to said second power supply voltage terminal, a gate coupled to said drain of said first N-channel transistor, and a drain coupled to said second source/drain terminal of said second N-channel transistor; a third P-channel transistor having a source coupled to said first power supply voltage terminal, a drain coupled to said drain of said third N-channel transistor and providing a CMOS-level output voltage thereon, and a gate for receiving said second input voltage; and BICMOS output driver means, coupled to said drain of said third P-channel transistor for providing an output signal of said ECL-to-CMOS level converter in response to a complement of said CMOS-level signal and for providing said output signal as said control signal.

Claim 14

The low power ECL-to-CMOS level converter of claim 10 wherein at least one of said P-channel transistors are enhancement-mode P-channel MOSFET transistors and at least one of said N-channel transistors are enhancement-mode N-channel MOSFET transistors.

Claim 15

The low power ECL-to-CMOS level converter of claim 10 wherein said output signal of said BICMOS output driver means is characterized as being a TTL-level signal.