Abstract This is a DMOS transistor and a method of forming a DMOS transistor structure. The method comprises: forming a polycrystalline silicon central gate region; forming a drain region in the substrate self-aligned to the central gate region; forming polycrystalline silicon gate sidewalls adjacent to the gate region; and forming a source region in the substrate self-aligned to the edges of the sidewalls. It can provide a channel region which is significantly longer (Ld) than it is in depth (essentially Lj) can be produced between the source region and the drain region, and thus the method provides an optimization of the transistor for lower on-resistance and thus a DMOS device having a MOS channel length longer than its parasitic JFET channel length. Preferably channel regions are formed which are 0.25-0.75 um in depth and the channel regions have an Ld of 1.0-2.5 um.
A method of forming a DMOS vertical transistor structure on a substrate, said method comprising: forming n- epi drain region on an n+ substrate; forming a polycrystalline silicon central gate region; forming a first region in the substrate self-aligned to said central gate region; forming polycrystalline silicon gate sidewalls adjacent to said gate region; and forming a source region in a portion of said first region self-aligned to the edges of the sidewalls, whereby a remaining portion of said first region providing a channel region which is significantly wider than it is high can be produced between said source region and said drain region and thus a DMOS vertical transistor structure having a MOS channel length longer than its parasitic JFET channel length, and thus the method provides an optimization of the DMOS vertical transistor structure for lower on-resistance.
Claim 2
Independent Claim
139 words
A method of forming a DMOS vertical transistor structure on a substrate, said method comprising: forming n- epi drain region on an n+ substrate; forming a polycrystalline silicon central gate region; forming a first region in the substrate self-aligned to said central gate region; forming polycrystalline silicon gate sidewalls adjacent to said gate region; and forming a source region in a portion of said first region self-aligned to the edges of the sidewalls, whereby a remaining portion of said first region providing a channel region which is significantly wider than it is high can be produced between said source region and said drain region and thus a DMOS vertical transistor structure having a MOS channel length longer than its parasitic JFET channel length, and thus the method provides an optimization of the DMOS vertical transistor structure for lower on-resistance.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein said central gate region and said gate sidewalls are n+ poly.
Claim 4
Dependent Claim
16 words
The method of claim 1, wherein channel regions are formed which are 0.25-0.75 um in depth.
Claim 5
Dependent Claim
15 words
The method of claim 3, wherein said channel regions have an Ld of 1.0-2.5 um.