US5201029A
Expired / Lapsed
US
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Digital data processing apparatus using daisy chain control
Assignee: US Philips Corp
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Filing: 1992-03-24
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Granted: 1993-04-06
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Expires: 2012-03-24
Abstract
Abstract Digital data processing apparatus for use as a three-layer perceptron comprises three sets of processing cells (29A-29D, 29E-29H, 29I-29L). The data inputs of the cells of each set are connected to a respective common data bus (30,32,33) and the data outputs of the cells of each set are connected to a respective common data bus (32,33,34). Input data applied sequentially to the input bus (30) are processed in parallel by the cells (29A-29D) of the first set under the control of a clock pulse generator arrangement (35) which controls synchronized read-out of respective weighting factors from a store included in each cell, accumulation of the thus weighted items of input data, latching of the processing result in each cell, and subsequent read-out of the latched results onto the relevant output bus (32). The read-out results constitute input data for the cells (29E-29H) of the next set, which operate in the same way, as do the cells (29I-29L) of the final set. As an alternative a single set may be used recursively.
Inventors
- 👤 John Jackson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:36
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/04; G06N3/0499; G06N3/06; G06N3/063
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
325 words
Digital data processing apparatus comprising a) a common input for receiving a set of sequential input digital data items; b) a common output c) a set of digital data processing cells for processing the set of sequential input digital data items, each cell comprising i) respective input means coupled with the common input for receiving the set of sequential input data items, so that all of the ells process the same data, ii) a respective output for supplying a respective item of digital output data to the common output; iii) a respective operand store comprising a respective plurality of storage locations, each storage location being for storing a respective operand; iv) a respective digital multiplier, having a first input coupled to the respective input means and a second input coupled to a data output of the respective operand store, for multiplying successive items of the set of sequential input digital data items by the respective operands; v) a respective accumulator, having a data input coupled to an output of the respective multiplier, for accumulating results of multiplications performed by the respective multiplier; vi) a respective latch arrangement for storing and outputting the respective item of digital output data; and vii) respective data transfer means, coupling an output of the respective accumulator to a data input of the respective latch arrangement, having a non-linear characteristic transfer function; d) clock pulse generator means, coupled to the respective operand stores and the respective latch arrangements, for causing: i) the storage locations, of each operand store, to output their respective operands in a first predetermined order and according to a timing which is coordinated with timings of output of corresponding respective operands from storage locations of the other operand stores; and ii) the latch arrangements to output their contents onto the common output in a second predetermined order, so that the output from each cell is presented to the common output in turn, whereby no bus arbitration is needed.
Claim 2
Dependent Claim
325 words
Digital data processing apparatus comprising a) a common input for receiving a set of sequential input digital data items; b) a common output c) a set of digital data processing cells for processing the set of sequential input digital data items, each cell comprising i) respective input means coupled with the common input for receiving the set of sequential input data items, so that all of the ells process the same data, ii) a respective output for supplying a respective item of digital output data to the common output; iii) a respective operand store comprising a respective plurality of storage locations, each storage location being for storing a respective operand; iv) a respective digital multiplier, having a first input coupled to the respective input means and a second input coupled to a data output of the respective operand store, for multiplying successive items of the set of sequential input digital data items by the respective operands; v) a respective accumulator, having a data input coupled to an output of the respective multiplier, for accumulating results of multiplications performed by the respective multiplier; vi) a respective latch arrangement for storing and outputting the respective item of digital output data; and vii) respective data transfer means, coupling an output of the respective accumulator to a data input of the respective latch arrangement, having a non-linear characteristic transfer function; d) clock pulse generator means, coupled to the respective operand stores and the respective latch arrangements, for causing: i) the storage locations, of each operand store, to output their respective operands in a first predetermined order and according to a timing which is coordinated with timings of output of corresponding respective operands from storage locations of the other operand stores; and ii) the latch arrangements to output their contents onto the common output in a second predetermined order, so that the output from each cell is presented to the common output in turn, whereby no bus arbitration is needed.
Claim 3
Dependent Claim
26 words
Apparatus as claimed in claim 1, wherein said common data output constitutes the common data input of a further such set of digital data processing cells.
Claim 4
Dependent Claim
33 words
The apparatus of claim 2 wherein the clock pulse generating arrangement causes the latch arrangements to output their contents according to a timing which is coordinated with the output of the respective operands.
Claim 5
Dependent Claim
24 words
apparatus as claimed in claim 1 wherein said common data output feeds back to said common data input, so that said cells operate recursively.
Claim 6
Dependent Claim
33 words
The apparatus of claim 4 wherein the clock pulse generating arrangement causes the latch arrangements to output their contents according to a timing which is coordinated with the output of the respective operands.
Claim 7
Dependent Claim
54 words
A digital data processing system comprising a plurality of apparatuses as claimed in claim 1, including a first apparatus and at least one next apparatus, arranged so that the common input of each next apparatus is the common output of a previous one of the apparatuses, whereby the apparatuses form layers of the system.
Claim 8
Dependent Claim
23 words
The apparatus of claim 1 wherein at least one of the cells comprises a control input for receiving control data from another cell.
Claim 9
Dependent Claim
23 words
The apparatus of claim 1 wherein at least one of the cells comprises a control output for supplying control data to another cell.
Claim 10
Dependent Claim
70 words
The apparatus of claim 1 wherein each of the cells comprises a respective control input for receiving control data; and a respective control output for supplying control data; and the cells are arranged in a daisy chain, with the respective control input of each next cell being coupled to the respective control output of a previous one of the cells, for sequential presentation of cell outputs to the common output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-05 | 1996-10-05 | 1997-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-05 | 2000-10-05 | 2001-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-05 | 2004-10-05 | 2005-04-06 | $7700.00 | Window Closed / Lapsed |