Sample and hold circuit for temporal associations in a neural network

Claim 2

An associative memory for memorizing and reconstructing time sequences of representations comprising: a neural network having a plurality of synapse inputs and an output providing an output pattern which varies in time, said neural network receiving a continuous sequence of data at said synapse inputs; a nonintegrating sample and hold device having a data input coupled to said output of said network for sampling and holding said output pattern for a certain time period so as to produce a delayed output pattern at a feedback output coupled to at least one of said plurality of synapse inputs to provide feedback of said output pattern to said neural network; and a means for synchronizing said feedback output of said sample and hold device with the time domain of said continuous sequence of data to allow recognition of said continuous sequence by said neural network.

Claim 3

The associative memory of claim 1 wherein said plurality of synapse inputs includes a temporal pattern input and a context input such that when said temporal pattern and said context are provided in association with said delayed output pattern, a next output pattern is evoked at said output of said network thereby triggering temporal recall of said time sequence.

Claim 4

The associative memory of claim 2 further comprising a clocking means for providing clock pulses to said device such that the period of said clock pulses determines said time period.

Claim 5

An associative memory for memorizing and reconstructing time sequences of representations comprising: a neural network having a plurality of synapse inputs for continuously receiving input data in the form of a temporal pattern, a context, and a delayed feedback of an output pattern, said neural network also having a plurality of neuron amplifiers and an output providing said output pattern which varies in time; a nonintegrating sample and hold device having a clock input, and a data input coupled to said output of said neural network for sampling and holding said output pattern for a certain time period so as to produce a delayed output pattern at a feedback output coupled to at least one of said plurality of synapse inputs to provide feedback of said output pattern to said neural network; and a clocking means coupled to said clock input for producing clock pulses to said device, said clock pulses providing said delayed feedback of said output pattern such that when said temporal pattern, said context, and said delayed feedback are synchronously, presented to said network, temporal recollection of said time sequence is evoked.

Claim 6

An associative memory for memorizing and reconstructing time sequences of representations comprising: a neural network having a plurality of synapse inputs for continuously receiving input data in the form of a temporal pattern, a context, and a delayed feedback of an output pattern, said neural network also having a plurality of neuron amplifiers and an output providing said output pattern which varies in time; a nonintegrating sample and hold device having a clock input, and a data input coupled to said output of said neural network for sampling and holding said output pattern for a certain time period so as to produce a delayed output pattern at a feedback output coupled to at least one of said plurality of synapse inputs to provide feedback of said output pattern to said neural network; and a clocking means coupled to said clock input for producing clock pulses to said device, said clock pulses providing said delayed feedback of said output pattern such that when said temporal pattern, said context, and said delayed feedback are synchronously, presented to said network, temporal recollection of said time sequence is evoked.

Claim 7

The associative memory of claim 4 wherein the period between said clock pulses determines the delay in said delayed feedback.

Claim 8

The associative memory of claim 5 further comprising a reset means for placing said at least one of said plurality of synapse inputs at a predetermined potential.

Claim 9

In a neural network having a plurality of neural amplifiers and a plurality of synapse inputs for receiving a continuous sequence of data in the form of a temporal pattern and a context, a nonintegrating sample and hold circuit providing delayed feedback of an output pattern from said network comprising: a first storage member having a clock input, a data input, and an output, said data input coupled to said output pattern of said network; a differential amplifier having a first input coupled to said output of said first storage member and a second input coupled to a reference potential, said amplifier also having a differential output providing single-to-double-ended conversion of said output pattern; a second storage member having a differential input coupled to said differential output of said amplifier, a clock input, and a differential word line coupled to at least one of said plurality of synapse inputs; a clocking means for providing a first clock pulse to said clock input of said first storage member and a second clock pulse to said clock input of said second storage member; said first storage member being responsive to said first pulse such that when said first pulse is absent said first storage member samples a present output pattern and when said first pulse is applied said first storage member holds said present output pattern, said second storage member being responsive to said second pulse such that when said second pulse is absent said second storage member holds a past one of said output pattern and when said second pulse is active said second storage member samples said present output pattern, amplified by said amplifier such that said word line output represents a delayed feedback of said output pattern, said first and second pulses being applied synchronous with said temporal pattern and said context inputs so as to facilitate temporal recall of a memorized sequence of representations.

Claim 10

In a neural network having a plurality of neural amplifiers and a plurality of synapse inputs for receiving a continuous sequence of data in the form of a temporal pattern and a context, a nonintegrating sample and hold circuit providing delayed feedback of an output pattern from said network comprising: a first storage member having a clock input, a data input, and an output, said data input coupled to said output pattern of said network; a differential amplifier having a first input coupled to said output of said first storage member and a second input coupled to a reference potential, said amplifier also having a differential output providing single-to-double-ended conversion of said output pattern; a second storage member having a differential input coupled to said differential output of said amplifier, a clock input, and a differential word line coupled to at least one of said plurality of synapse inputs; a clocking means for providing a first clock pulse to said clock input of said first storage member and a second clock pulse to said clock input of said second storage member; said first storage member being responsive to said first pulse such that when said first pulse is absent said first storage member samples a present output pattern and when said first pulse is applied said first storage member holds said present output pattern, said second storage member being responsive to said second pulse such that when said second pulse is absent said second storage member holds a past one of said output pattern and when said second pulse is active said second storage member samples said present output pattern, amplified by said amplifier such that said word line output represents a delayed feedback of said output pattern, said first and second pulses being applied synchronous with said temporal pattern and said context inputs so as to facilitate temporal recall of a memorized sequence of representations.

Claim 11

The sample and hold circuit of claim 7, wherein said first storage member comprises a transmission gate coupled in parallel to a capacitor in said second storage member comprises a pair of transmission gates each of which is coupled in parallel to a capacitor.

Claim 12

The sample and hold circuit of claim 7, further comprising a reset means coupled to said second storage member for placing a predetermined potential on said word line output.