Method for manufacturing a mask read only memory device

Claim 1

A method for manufacturing a mask read only memory device, comprising the step of: consecutively forming a first conductive layer and a first insulation layer over a top surface of a semiconductor substrate of a given conductivity type, said semiconductor substrate having a gate oxide layer formed thereon; forming a mask pattern of a word line in the order of odd numbers or even numbers; forming a second insulation layer positioned on a top surface and on a sidewall of said mask pattern and on a partial top surface of said first conductive layer; forming a third insulation layer over a top surface of said substrate and etching out said third insulation layer until said second insulation layer positioned on said mask pattern is sufficiently exposed; and consecutively etching out a partial top surface of said second insulation layer and said first conductive layer by using a remaining third insulation layer as a mask, so as to form a first conductive layer pattern separated from each other with spacing corresponding to a thickness of said second insulation layer.

Claim 2

A method for manufacturing a mask read only memory device, comprising the step of: consecutively forming a first conductive layer and a first insulation layer over a top surface of a semiconductor substrate of a given conductivity type, said semiconductor substrate having a gate oxide layer formed thereon; forming a mask pattern of a word line in the order of odd numbers or even numbers; forming a second insulation layer positioned on a top surface and on a sidewall of said mask pattern and on a partial top surface of said first conductive layer; forming a third insulation layer over a top surface of said substrate and etching out said third insulation layer until said second insulation layer positioned on said mask pattern is sufficiently exposed; and consecutively etching out a partial top surface of said second insulation layer and said first conductive layer by using a remaining third insulation layer as a mask, so as to form a first conductive layer pattern separated from each other with spacing corresponding to a thickness of said second insulation layer.

Claim 4

The method as claimed in claim wherein said first conductive layer is of tungsten silicide, titanium silicide or tantalum silicide.

Claim 11

The method as claimed in claim wherein said first insulation layer and said second insulation layer are adjacently formed on another, on a top surface of said first conductive layer pattern, after forming said first conductive layer pattern.

Claim 18

A method for manufacturing a NAND logic mask read only memory device having a memory array including a plurality of memory strings connected to a bit line, in parallel and a memory cell disposed in a same row sharing a word line, said memory string being serially connected between said bit line and a ground voltage terminal, said method comprising the steps of: consecutively forming a first conductive layer, a first insulation layer and a second conductive layer over a top surface of a semiconductor substrate of a given conductivity type, said substrate having an isolation region for isolating said memory string and a gate oxide layer formed thereon; etching out a given region of said first insulation layer and said second conductive layer formed over a top surface of said substrate until said first conductive layer is exposed, to thereby form a pattern of said second conductive layer and said first insulation layer; forming a second insulation layer on a top surface of said first conductive layer, on a top surface and on a sidewall of a patterned second conductive layer and on a side wall of a patterned first insulation layer, applying a first photoresist over a top surface of said substrate and etching out said first photoresist until a surface of said second insulation layer disposed on said second conductive layer is exposed; forming a pattern of a word line by removing an exposed second insulation layer and first conductive layer positioned under a removed second insulation layer and removing a patterned second conductive layer; removing said first photoresist, applying a second photoresist over the partial top surface of said substrate and etching out an exposed first insulation layer and a remaining first conductive layer positioned under a removed first insulation layer, to thereby form a pattern of a memory string select line; removing said second photoresist, defining an ion implantation region in order to ion implant a given impurity and performing an oxidation process for activating said ion implantation region, to thereby form a third insulation layer on a sidewall of said insulation layer and word line; exposing a corresponding word line having a first insulation layer formed thereon among word lines of a cell to be programmed, by a first photolithography process and removing an exposed first insulation layer; exposing a corresponding word line having a second insulation layer formed thereon among word lines of a cell to be programmed, by a second photolithography process and removing an exposed second insulation layer; and ion implanting a given impurity over the entire surface of said substrate, to thereby form program data.

Claim 19

A method for manufacturing a NAND logic mask read only memory device having a memory array including a plurality of memory strings connected to a bit line, in parallel and a memory cell disposed in a same row sharing a word line, said memory string being serially connected between said bit line and a ground voltage terminal, said method comprising the steps of: consecutively forming a first conductive layer, a first insulation layer and a second conductive layer over a top surface of a semiconductor substrate of a given conductivity type, said substrate having an isolation region for isolating said memory string and a gate oxide layer formed thereon; etching out a given region of said first insulation layer and said second conductive layer formed over a top surface of said substrate until said first conductive layer is exposed, to thereby form a pattern of said second conductive layer and said first insulation layer; forming a second insulation layer on a top surface of said first conductive layer, on a top surface and on a sidewall of a patterned second conductive layer and on a side wall of a patterned first insulation layer, applying a first photoresist over a top surface of said substrate and etching out said first photoresist until a surface of said second insulation layer disposed on said second conductive layer is exposed; forming a pattern of a word line by removing an exposed second insulation layer and first conductive layer positioned under a removed second insulation layer and removing a patterned second conductive layer; removing said first photoresist, applying a second photoresist over the partial top surface of said substrate and etching out an exposed first insulation layer and a remaining first conductive layer positioned under a removed first insulation layer, to thereby form a pattern of a memory string select line; removing said second photoresist, defining an ion implantation region in order to ion implant a given impurity and performing an oxidation process for activating said ion implantation region, to thereby form a third insulation layer on a sidewall of said insulation layer and word line; exposing a corresponding word line having a first insulation layer formed thereon among word lines of a cell to be programmed, by a first photolithography process and removing an exposed first insulation layer; exposing a corresponding word line having a second insulation layer formed thereon among word lines of a cell to be programmed, by a second photolithography process and removing an exposed second insulation layer; and ion implanting a given impurity over the entire surface of said substrate, to thereby form program data.

Claim 35

A method for manufacturing a NOR logic mask read only memory device having a word line extending to a first direction of a transverse direction and being disposed in parallel to a second direction of a longitudinal direction and a bit line extending to said second direction, being disposed in parallel to said first direction and being formed with a diffusion region of impurity having a given conductivity type, said method comprising the steps of: forming a first conductive layer on a top surface of a semiconductor of a given conductivity and forming a first insulation layer, said semiconductor substrate having a gate oxide layer formed thereon; patterning said first insulation layer along a word line in the order of even numbers or odd numbers; forming a second insulation layer over the entire surface of said semiconductor substrate; forming a third insulation layer over the entire surface of said semiconductor substrate and etching out said third insulation layer until a top surface of said second insulation layer positioned on a patterned first insulation layer is sufficiently exposed; etching out the partial top surface of said second insulation layer and the first conductive layer positioned under a removed second insulation layer, to thereby form a word line; removing said third insulation layer and forming a fourth insulation layer over the entire surface of said semiconductor substrate; exposing a corresponding word line having a first insulation layer formed thereon among word lines of a cell to be programmed, by a first photolithography process and removing an exposed first insulation layer. exposing a corresponding word line having a second insulation layer formed thereon among word lines of a cell to be programmed, by a second photolithography process and removing an exposed second insulation layer. ion implanting a given impurity over the entire surface of said substrate, to thereby form program data.

Claim 36

A method for manufacturing a NOR logic mask read only memory device having a word line extending to a first direction of a transverse direction and being disposed in parallel to a second direction of a longitudinal direction and a bit line extending to said second direction, being disposed in parallel to said first direction and being formed with a diffusion region of impurity having a given conductivity type, said method comprising the steps of: forming a first conductive layer on a top surface of a semiconductor of a given conductivity and forming a first insulation layer, said semiconductor substrate having a gate oxide layer formed thereon; patterning said first insulation layer along a word line in the order of even numbers or odd numbers; forming a second insulation layer over the entire surface of said semiconductor substrate; forming a third insulation layer over the entire surface of said semiconductor substrate and etching out said third insulation layer until a top surface of said second insulation layer positioned on a patterned first insulation layer is sufficiently exposed; etching out the partial top surface of said second insulation layer and the first conductive layer positioned under a removed second insulation layer, to thereby form a word line; removing said third insulation layer and forming a fourth insulation layer over the entire surface of said semiconductor substrate; exposing a corresponding word line having a first insulation layer formed thereon among word lines of a cell to be programmed, by a first photolithography process and removing an exposed first insulation layer. exposing a corresponding word line having a second insulation layer formed thereon among word lines of a cell to be programmed, by a second photolithography process and removing an exposed second insulation layer. ion implanting a given impurity over the entire surface of said substrate, to thereby form program data.