US5199052A
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US
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Reload timer circuit
Assignee: Fujitsu Ltd
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Filing: 1991-07-01
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Granted: 1993-03-30
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Expires: 2011-07-01
Abstract
Abstract A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.
Inventors
- 👤 Atsushi Fujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:36
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/665
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
107 words
A reload timer circuit comprising: an n-bit counter circuit for receiving input data of n bits and providing count data of n bits based upon a counting operation thereof in response to a counter operation signal (S2); an n-bit timer circuit for receiving n-bit count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit counter circuit with the timer period signal as a counting operation signal, said timer period signal controlling the period of each pulse of the n-bit timer circuit.
Claim 2
Dependent Claim
107 words
A reload timer circuit comprising: an n-bit counter circuit for receiving input data of n bits and providing count data of n bits based upon a counting operation thereof in response to a counter operation signal (S2); an n-bit timer circuit for receiving n-bit count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit counter circuit with the timer period signal as a counting operation signal, said timer period signal controlling the period of each pulse of the n-bit timer circuit.
Claim 3
Dependent Claim
26 words
A reload timer circuit according to claim 1, wherein said counter circuit counts up a counter value thereof in response to said counting operation signal (S2).
Claim 4
Dependent Claim
26 words
A reload timer circuit according to claim 1, wherein said counter circuit counts down a counter value therof in response to said counting operation signal (S2).
Claim 5
Dependent Claim
52 words
A reload timer circuit according to claim 1, wherein said counter circuit comprises an up/down controlling means for selecting any one of a counting-up function and a counting-down function of the counter circuit in response to an up/down counter (U/D) indicating the counting-up operation or the counting-down operation of the counter circuit.
Claim 6
Dependent Claim
48 words
A reload timer circuit according to claim 1, wherein said counter circuit selectively operates for counting-up operation or the counting down operation in response to an up/down counter (U/D) indicating the counting-up operation or the counting down operation of the counter circuit and said counting operation signal (S2).
Claim 7
Dependent Claim
48 words
A reload timer circuit as set forth in claim 5, wherein the n-bit up/down counter circuit provides the n-bit up/down count data according to the n-bit input data as well as data provided by a means for determining the direction of a change in the n-bit input data.
Claim 8
Dependent Claim
29 words
A reload timer circuit as set forth in claim 6, wherein the means for determining the direction of a change in the n-bit input data is an up/down counter.
Claim 9
Dependent Claim
33 words
A reload timer circuit as set forth in claim 6, wherein the means for determining the direction of a change in the n-bit input data is an operation means incorporating a proper program.
Claim 10
Dependent Claim
42 words
A reload timer circuit as set forth in claim 5, wherein the timer period setting means changes the n-bit up/down count data stored in the n-bit up/down counter circuit by a predetermined value in response to a generation of the overflow signal.
Claim 11
Dependent Claim
41 words
A reload timer circuit as set forth in claim 5, wherein the n-bit timer circuit carries out a count-up or count-down operation from an initial value to a predetermined value, and generates the overflow signal when the predetermined value is attained.
Claim 12
Dependent Claim
60 words
A reload timer circuit as set forth in claim 5, wherein the timer period setting means transfers the n-bit up/down count data stored in the n-bit up/down counter circuit to the n-bit timer circuit in response to the overflow signal, and after the completion of the transfer, rewrites the n-bit up/down count data stored in the n-bit up/down counter circuit.
Claim 13
Dependent Claim
22 words
A reload timer circuit as set forth in claim 11, wherein the timer period setting means includes at least a delay circuit.
Claim 14
Dependent Claim
52 words
A reload timer circuit as set forth in claim 9, wherein the timer period setting means changes the n-bit up/down count data stored in the n-bit up/down counter circuit by a predetermined value in response to a generation of the overflow signal until the n-bit up/down count data reaches a predetermined limit.
Claim 15
Dependent Claim
63 words
A reload timer circuit as set forth in claim 13, wherein the timer period setting means changes the n-bit up/down count data stored in the n-bit up/down counter circuit by a predetermined value in response to a generation of the overflow signal until the n-bit up/down count data reaches the predetermined limit, and thereafter, repeats this process after initializing the up/down count data.
Claim 16
Dependent Claim
65 words
A reload timer circuit as set forth in claim 13, wherein the timer period setting means includes a stop setting register for storing predetermined n-bit data used to stop changing the n-bit up/down count data, and providing a function to stop changing the value of the data to the n-bit up/down counter circuit when the predetermined n-bit data coincide with the n-bit up/down count data.
Claim 17
Dependent Claim
61 words
A reload timer circuit as set forth in claim 13, wherein the timer period setting means is connected to a proper operation means, the operation means including a counter for storing a predetermined initial value, decrementing the counter whenever the overflow signal is generated, and stopping the function of the timer period setting means when the counter counts a predetermined value.
Claim 18
Dependent Claim
56 words
A reload timer circuit as set forth in claim 10, wherein said reload timer circuit is connected to a processing means (CPU) through a data-bus and thereby an initial value of the data being set in said n-bit up/down counter circuit thereof from said processing means (CPU) and an up/down controlling signal (U/D) being supplied thereto.
Claim 19
Dependent Claim
43 words
A reload timer circuit as set forth in claim 15, wherein said reload timer circuit is connected to a processing means (CPU) through a data-bus and thereby a predetermined n-bit data is supplied from said processing means (CPU) to a stop value register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |