US5063355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timer circuit
Assignee: Omron Corp
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Filing: 1990-03-09
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Granted: 1991-11-05
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Expires: 2010-03-09
Abstract
Abstract The timer circuit according to this invention has a first circuit block to which a source voltage is applied at all times and which includes a memory circuit which is set when an input signal is applied thereto. The timer circuit also has a reference voltage circuit which outputs a reference voltage when the memory circuit is set and which ceases to output the reference voltage when the memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, and a counter which begins to count the train of pulse signals after the reference voltage is outputted. The timer circuit further includes a second circuit block which includes a signal processing circuit which outputs a timer signal while the counter is counting. A reference voltage is supplied from the reference voltage circuit to the components of the second circuit block while the memory circuit remains set and the memory circuit is reset in response to a time-out signal from the counter.
Inventors
- 👤 Kazuo Sasaki
- 👤 Hidetoshi Matsumoto
- 👤 Taneji Ohoka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:22
CPC Classifications
G; G04; G04G; G04G19/00; G04G19/12; G04F; G04F1/00; G04F1/005
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
166 words
A timer circuit comprising: a first circuit block which is supplied with a source voltage at all times and comprising a memory circuit which is set when an input signal is applied thereto; a second circuit block comprising a reference voltage circuit which outputs a reference voltage when said memory circuit is set and which ceases to output the reference voltage when said memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, a counter which starts counting said train of pulse signals when said reference voltage is outputted and which stops counting when a predetermined number of said pulse signals have been counted, and a signal processing circuit which outputs a timer signal while said counter is counting; wherein said reference voltage supplied by said reference voltage circuit is applied to power said second circuit block while the memory circuit remains set, wherein said memory circuit is reset in response to a time-out signal from said counter.
Claim 2
Dependent Claim
166 words
A timer circuit comprising: a first circuit block which is supplied with a source voltage at all times and comprising a memory circuit which is set when an input signal is applied thereto; a second circuit block comprising a reference voltage circuit which outputs a reference voltage when said memory circuit is set and which ceases to output the reference voltage when said memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, a counter which starts counting said train of pulse signals when said reference voltage is outputted and which stops counting when a predetermined number of said pulse signals have been counted, and a signal processing circuit which outputs a timer signal while said counter is counting; wherein said reference voltage supplied by said reference voltage circuit is applied to power said second circuit block while the memory circuit remains set, wherein said memory circuit is reset in response to a time-out signal from said counter.
Claim 3
Dependent Claim
14 words
A timer circuit according to claim 1, where said memory circuit comprises a flip-flop.
Claim 4
Dependent Claim
15 words
A timer circuit according to claim 1, where said reference voltage circuit comprises a batter.
Claim 5
Dependent Claim
209 words
A timer circuit comprising: a first circuit block which is supplied with a source voltage at all times and comprising a memory circuit which is set by input means for receiving input signals, said input means comprising a plurality of input terminal circuits to receive input signals; a second circuit block comprising a reference voltage circuit which outputs a reference voltage when said memory circuit is set and which ceases to output the reference voltage when said memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, a counter which starts counting said train of pulse signals when said reference voltage is outputted and which stops counting when a predetermined number of said pulse signals have been counted, and a signal processing circuit having timer signal output means which provides timer signal output while said counter is counting, said timer signal output means comprising a plurality of output terminal circuits to produce timer signals output signals corresponding respectively to said input signals; wherein said reference voltage supplied by said reference voltage circuit is applied to power said second circuit block while the memory circuit remains set, wherein said memory circuit is reset in response to a time-out signal from said counter.
Claim 6
Dependent Claim
209 words
A timer circuit comprising: a first circuit block which is supplied with a source voltage at all times and comprising a memory circuit which is set by input means for receiving input signals, said input means comprising a plurality of input terminal circuits to receive input signals; a second circuit block comprising a reference voltage circuit which outputs a reference voltage when said memory circuit is set and which ceases to output the reference voltage when said memory circuit is reset, an oscillation circuit which outputs a train of pulse signals in a predetermined cycle, a counter which starts counting said train of pulse signals when said reference voltage is outputted and which stops counting when a predetermined number of said pulse signals have been counted, and a signal processing circuit having timer signal output means which provides timer signal output while said counter is counting, said timer signal output means comprising a plurality of output terminal circuits to produce timer signals output signals corresponding respectively to said input signals; wherein said reference voltage supplied by said reference voltage circuit is applied to power said second circuit block while the memory circuit remains set, wherein said memory circuit is reset in response to a time-out signal from said counter.
Claim 7
Dependent Claim
14 words
A timer circuit according to claim 4, where said memory circuit comprises a flip-flop.
Claim 8
Dependent Claim
15 words
A timer circuit according to claim 4, where said reference voltage circuit comprises a battery.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-11-04 | 1995-05-06 | 1995-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-11-04 | 1999-05-06 | 1999-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-11-04 | 2003-05-06 | 2003-11-05 | $7700.00 | Window Closed / Lapsed |