Patent US3882126A successfully refreshed from Google Patents.
Patent US5199034A successfully refreshed from Google Patents.
US5199034A
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Apparatus and method for testing semiconductors for cell to bitline leakage
Assignee: Texas Instruments Inc
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Filing: 1990-12-31
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Granted: 1993-03-30
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Expires: 2010-12-31
Abstract
Abstract A method of testing for cell to bitline leakage using an improved algorithm is disclosed. A selected portion of the bitlines, both true and complement, are changed. In this manner, the entire memory can be tested without regard to memory size. The prior algorithm used to perform this same function on a megabit dram would take about 570 seconds. The new procedure performs the same function in a more efficient manner, resulting in a test time of approximately 2.8 seconds which is over 200 times faster.
Inventors
- 👤 Ignatius Yeo
- 👤 Eileen W. L. Kam
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:38
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C29/56; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
335 words
A method for testing leakage between cells and bitlines in a memory, said memory having a plurality of columns arranged as bitlines and as bitline complements, each said column connected to a cell in each row and wherein all of the cells of certain rows are connected to respective bitline columns and all of the cells of certain other rows are connected to respective complement bitline columns, said method comprising the steps of: 1) writing a background of data to all of said cells; 2) writing one of said bitline connected rows with the complement of said data; 3) reading said one bitline row for a period of time corresponding to the refresh time of said memory; 4) writing said one bitline row with said data; 5) reading the entire memory array to ascertain if any cell now contains any complementary data; 6) writing one of said complement bitline rows with said complement of said data; 7) reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; 8) writing said last-mentioned bitline row with said data; 9) reading the entire memory array to ascertain if any cell now contains any complementary data; 10) writing a background of complement data to all of said cells; 11) writing one of said bitline connected rows with said data; 12) reading said one bitline row for a period of time corresponding to the refresh time of said memory; 13) writing said one bitline row with said data complement; 14) reading the entire memory array to ascertain if any cell now contains any data which is not said data complement; 15) writing one of said complement bitline rows with said data; 16) reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; 17) writing said last-mentioned bitline row with said data complement; and 18) reading the entire memory array to ascertain if any cell now contains any data which is not said data complement.
Claim 2
Independent Claim
335 words
A method for testing leakage between cells and bitlines in a memory, said memory having a plurality of columns arranged as bitlines and as bitline complements, each said column connected to a cell in each row and wherein all of the cells of certain rows are connected to respective bitline columns and all of the cells of certain other rows are connected to respective complement bitline columns, said method comprising the steps of: 1) writing a background of data to all of said cells; 2) writing one of said bitline connected rows with the complement of said data; 3) reading said one bitline row for a period of time corresponding to the refresh time of said memory; 4) writing said one bitline row with said data; 5) reading the entire memory array to ascertain if any cell now contains any complementary data; 6) writing one of said complement bitline rows with said complement of said data; 7) reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; 8) writing said last-mentioned bitline row with said data; 9) reading the entire memory array to ascertain if any cell now contains any complementary data; 10) writing a background of complement data to all of said cells; 11) writing one of said bitline connected rows with said data; 12) reading said one bitline row for a period of time corresponding to the refresh time of said memory; 13) writing said one bitline row with said data complement; 14) reading the entire memory array to ascertain if any cell now contains any data which is not said data complement; 15) writing one of said complement bitline rows with said data; 16) reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; 17) writing said last-mentioned bitline row with said data complement; and 18) reading the entire memory array to ascertain if any cell now contains any data which is not said data complement.
Claim 3
Dependent Claim
45 words
The method set forth in claim 1 wherein said columns are divided into sections by a sense amplifier and wherein said method includes the steps of: first performing said eighteen steps on a first section and then performing said eighteen steps on a second section.
Claim 4
Dependent Claim
27 words
The method set forth in claim 2 wherein said rows connected to said bitlines and said rows connected to said complement bitlines are alternating with each other.
Claim 5
Dependent Claim
31 words
The method set forth in claim 2 wherein said steps 1-9 for both claims 1 and 2 are performed prior to the performance of steps 10-18 of claims 1 and 2.
Claim 6
Dependent Claim
359 words
A test system for testing leakage between cells and bitlines in a memory, said memory having a plurality of columns arranged as bitlines and as bitline complements, each said column connected to a cell in each row and wherein all of the cells of certain rows are connected to respective bitline columns and all of the cells of certain other rows are connected to respective complement bitline columns, said system comprising a cpu connectable to a memory and including circuitry for writing a background of data to all of said cells; circuitry for writing one of said bitline connected rows with the complement of said data; circuitry for reading said one bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said one bitline row with said data; circuitry for reading the entire memory array to ascertain if any cell now contains any complementary data; circuitry for writing one of said complement bitline rows with said complement of said data; circuitry for reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said last-mentioned bitline row with said data; circuitry for reading the entire memory array to ascertain if any cell now contains any complementary data; circuitry for writing a background of complement data to all of said cells; circuitry for writing one of said bitline connected rows with said data; circuitry for reading said one bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said one bitline row with said data complement; circuitry for reading the entire memory array to ascertain if any cell now contains any data which is not said data complement; circuitry for writing one of said complement bitline rows with said data; circuitry for reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said last-mentioned bitline row with said data complement; and circuitry for reading the entire memory array to ascertain if any cell now contains any data which is not said data complement.
Claim 7
Dependent Claim
359 words
A test system for testing leakage between cells and bitlines in a memory, said memory having a plurality of columns arranged as bitlines and as bitline complements, each said column connected to a cell in each row and wherein all of the cells of certain rows are connected to respective bitline columns and all of the cells of certain other rows are connected to respective complement bitline columns, said system comprising a cpu connectable to a memory and including circuitry for writing a background of data to all of said cells; circuitry for writing one of said bitline connected rows with the complement of said data; circuitry for reading said one bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said one bitline row with said data; circuitry for reading the entire memory array to ascertain if any cell now contains any complementary data; circuitry for writing one of said complement bitline rows with said complement of said data; circuitry for reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said last-mentioned bitline row with said data; circuitry for reading the entire memory array to ascertain if any cell now contains any complementary data; circuitry for writing a background of complement data to all of said cells; circuitry for writing one of said bitline connected rows with said data; circuitry for reading said one bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said one bitline row with said data complement; circuitry for reading the entire memory array to ascertain if any cell now contains any data which is not said data complement; circuitry for writing one of said complement bitline rows with said data; circuitry for reading said last-mentioned bitline row for a period of time corresponding to the refresh time of said memory; circuitry for writing said last-mentioned bitline row with said data complement; and circuitry for reading the entire memory array to ascertain if any cell now contains any data which is not said data complement.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |