Patent US5199032A successfully refreshed from Google Patents.
US5199032A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcontroller having an EPROM with a low voltage program inhibit circuit
Assignee: NXP USA Inc
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Filing: 1990-09-04
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Granted: 1993-03-30
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Expires: 2010-09-04
Abstract
Abstract A microcontroller is provided having an on-chip electrically erasable programmable read-only-memory (EEPROM), which is user programmable via a programming register. The microcontroller includes a low voltage program inhibit (LVPI) circuit which is combined with the existing EEPROM design. By integrating the LVPI circuit into the EEPROM, the EEPROM may be protected without disabling the entire data processing system. If the supply voltage (VDD) falls below a predetermined voltage level, the LVPI circuit inhibits the use of the EEPROM programming register, thereby preventing the CPU from programming or erasing the EEPROM. A comparator in the LVPI circuit compares a precision reference voltage to a voltage divided off of the power supply (VDD), and provides a output signal to the EEPROM programming register. During normal operation, the comparator output signal is a logic low, which enables the user to program or erase the EEPROM, via the programming register. When the supply voltage is below the predetermined safe level, the comparator output signal is a logic high signal, which sets a control bit in the programming register. When set, the control bit clears the remaining bits in the programming register, thereby disabling a charge pump, and preventing any further EEPROM programming.
Inventors
- 👤 Robert W. Sparks
- 👤 Gregory A. Racino
- 👤 Brian R. Gardner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:59
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G06; G06F; G06F11/00; G06F11/004; G11C16/10; G11C16/22; G11C16/225; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
291 words
In a data processing system having a processor, an electrically alterable memory, and a communications bus for communicating therebetween, protection means included in said memory for inhibiting the alteration of said memory when a supply voltage falls below a specified voltage level, said protection means comprising: first means for providing a reference voltage; second means coupled to said first means for comparing a second voltage generated from said supply voltage to said reference voltage, and for providing an output signal, said output signal having a first logic value when said second voltage is larger in magnitude than said reference voltage, and a second logic value when said second voltage is smaller in magnitude that said reference voltage; third means coupled to said second means for supplying said second voltage to said second means, said third means operating to insure that when said supply voltage remains above the specified voltage level, said second voltage supplied to said second means is larger in magnitude than said reference voltage, and when said supply voltage falls below the specified voltage level, said second voltage supplied to said second means is smaller in magnitude that said reference voltage; and fourth means coupled to said second means for storing a plurality of control bits for controlling programming of said memory, said fourth means inhibiting the alteration of said memory when said output signal is said second logic value, without disabling said processor from accessing information stored in said memory during performance by said processor of other data processing operations, and enabling the programming of said memory when said output signal is said first logic value, said fourth means controlling programming of said memory by manipulating said control bits based upon the logic value of said output signal.
Claim 2
Dependent Claim
291 words
In a data processing system having a processor, an electrically alterable memory, and a communications bus for communicating therebetween, protection means included in said memory for inhibiting the alteration of said memory when a supply voltage falls below a specified voltage level, said protection means comprising: first means for providing a reference voltage; second means coupled to said first means for comparing a second voltage generated from said supply voltage to said reference voltage, and for providing an output signal, said output signal having a first logic value when said second voltage is larger in magnitude than said reference voltage, and a second logic value when said second voltage is smaller in magnitude that said reference voltage; third means coupled to said second means for supplying said second voltage to said second means, said third means operating to insure that when said supply voltage remains above the specified voltage level, said second voltage supplied to said second means is larger in magnitude than said reference voltage, and when said supply voltage falls below the specified voltage level, said second voltage supplied to said second means is smaller in magnitude that said reference voltage; and fourth means coupled to said second means for storing a plurality of control bits for controlling programming of said memory, said fourth means inhibiting the alteration of said memory when said output signal is said second logic value, without disabling said processor from accessing information stored in said memory during performance by said processor of other data processing operations, and enabling the programming of said memory when said output signal is said first logic value, said fourth means controlling programming of said memory by manipulating said control bits based upon the logic value of said output signal.
Claim 3
Dependent Claim
15 words
The protection means of claim 1 wherein said first means comprises a voltage reference circuit.
Claim 4
Dependent Claim
36 words
The protection means of claim 2 wherein said output signal provided by said second means clears said control bits when said supply voltage falls below said specified voltage level, thereby inhibiting the programming of said memory.
Claim 5
Dependent Claim
88 words
The protection means of claim 3 wherein said fourth means comprises: register means for storing said plurality of control bits for programming and erasing a plurality of data bytes stored in said memory; ORing means coupled to said register means, said ORing means having a first input for receiving said output signal, a second input for receiving an internal reset signal provided by said processor, and an output for clearing said control bits stored in said register means, when said supply voltage falls below said specified voltage level.
Claim 6
Dependent Claim
28 words
The protection means of claim 4 wherein said fourth means resets said control bits in said register means, when said supply voltage falls below said specified voltage level.
Claim 7
Dependent Claim
220 words
In a data processing system having a processor, an electrically alterable memory, and a communications bus for communicating therebetween, protection means in said memory for inhibiting alteration of said memory when a supply voltage falls below a specified voltage level, said protection means comprising: detection means for detecting when said supply voltage falls below said specified voltage level, and for providing an output control signal, in response thereto; and programming means, coupled to said detection means, for storing a plurality of control bits for controlling alteration of said memory, and for inhibiting manipulation of said control bits, said programming means preventing said processor from altering said memory, in response to said output signal having a first logic value, without disabling said processor from accessing information stored in said memory during performance by said processor of other data processing operations, said programming means comprising: register means for storing said plurality of control bits for programming and erasing a plurality of data bytes stored in said memory; logic means coupled to said register means, said logic means having a first input for receiving said output signal, a second input for receiving an internal reset signal provided by said processor, and an output for clearing said control bits stored in said register means, when said supply voltage falls below said specified voltage level.
Claim 8
Dependent Claim
220 words
In a data processing system having a processor, an electrically alterable memory, and a communications bus for communicating therebetween, protection means in said memory for inhibiting alteration of said memory when a supply voltage falls below a specified voltage level, said protection means comprising: detection means for detecting when said supply voltage falls below said specified voltage level, and for providing an output control signal, in response thereto; and programming means, coupled to said detection means, for storing a plurality of control bits for controlling alteration of said memory, and for inhibiting manipulation of said control bits, said programming means preventing said processor from altering said memory, in response to said output signal having a first logic value, without disabling said processor from accessing information stored in said memory during performance by said processor of other data processing operations, said programming means comprising: register means for storing said plurality of control bits for programming and erasing a plurality of data bytes stored in said memory; logic means coupled to said register means, said logic means having a first input for receiving said output signal, a second input for receiving an internal reset signal provided by said processor, and an output for clearing said control bits stored in said register means, when said supply voltage falls below said specified voltage level.
Claim 9
Dependent Claim
90 words
The protection means of claim 6 wherein said detection means comprises: first means for providing a reference voltage; second means coupled to said first means for comparing a second voltage generated from said supply voltage to said reference voltage, and for providing an output signal indicating whether said second voltage is larger or smaller in magnitude than said reference voltage; third means coupled to said second means for supplying said second voltage to said second means, said third means indicating when said supply voltage falls below said specified voltage level.
Claim 10
Dependent Claim
15 words
The protection means of claim 7 wherein said first means comprise a voltage reference circuit.
Claim 11
Dependent Claim
14 words
The protection means of claim 7 wherein said second means comprises a voltage comparator.
Claim 12
Dependent Claim
74 words
The protection means of claim 7 wherein said third means comprises a hysteresis mechanism, said hysteresis mechanism operating to insure that when said supply voltage remains above the specified voltage level, said second voltage supplied to said second means is larger in magnitude than said reference voltage, and when said supply voltage falls below the specified voltage level, said second voltage supplied to said second means is smaller in magnitude that said reference voltage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |