Packaged semiconductor device and electronic device module including same

Claim 2

A packaged semiconductor device comprising: a semiconductor chip having first and second main surfaces and electrode pads formed on said first surface; a plurality of electrode leads; a plurality of connection conductors for interconnecting said electrode pads and said electrode leads; a heat sink block attached to said second main surface of said semiconductor chip and consisting of a first portion to which said second main surface of said semiconductor chip is attached and a second portion which extends from said first portion away from said semiconductor chip; and a mold block having a first mold block portion, which encloses said semiconductor chip including said electrode pads, said plurality of electrode leads, said plurality of connection conductors and said first portion of said heat sink block, and a second mold block portion which encloses said second portion of said heat sink block, said second mold block portion being smaller than said first mold block portion and extending from said first mold block portion to form said mold block which has a "T"-shaped cross-section, with said first mold block portion forming a horizontal segment of "T", wherein said second portion of said heat sink block has an exposed surface which is not enclosed by said second mold block portion.

Claim 3

A packaged semiconductor device according to claim 1, wherein each of said electrode leads has a free end surface portion that is positioned at a level farther away from said semiconductor chip than a level at which a boundary between said first and second mold block portion is positioned.

Claim 4

A packaged semiconductor device according to claim 1, wherein said second mold block portion has side faces which are tapered so that an intersection of the horizontal segment and a vertical segment in said "T"-shaped cross-section of said mold block is wider than the free end of said second mold block.

Claim 5

A packaged semiconductor device according to claim 1, wherein said semiconductor chip is a power field effect transistor having source, drain and gate regions, and at least one of said plurality of electrode leads electrically connected to said source, drain and gate regions, respectively, having a comb-like structure with a plurality of juxtaposed electrode leads electrically connected to one another.

Claim 6

An electronic device module comprising: a support plate; an electrically insulating substrate having a first metallized surface and a second surface provided with a conductor pattern, said substrate being placed on said support plate with said first metallized surface opposed to said support plate, at least one through-hole being formed in said substrate; and a packaged semiconductor device comprising: a semiconductor chip, a plurality of electrode leads, a plurality of connection conductors for interconnecting said semiconductor chip and said electrode leads, a heat sink blood attached to said chip and consisting of a first portion to which said second main surface of said semiconductor chip is attached and a second portion which extends from said first portion away from said semiconductor chip, and a mold block having a first mold block portion, which encloses said semiconductor chip, said plurality of electrode leads, said plurality of connection conductors and said first portion of said heat sink block, and a second mold block portion which encloses said second portion of said heat sink block, said second mold block portion being smaller than said first mold block portion and extending from said first mold block portion to form said mold block which has a "T"-shaped cross-section, with said first mold block portion forming a horizontal segment of "T", wherein said second portion of said heat sink block has an exposed surface which is not enclosed by said second mold block portion, and wherein each of said electrode leads has a free end surface portion that is positioned at a level farther away from said semiconductor chip than a level at which a boundary between said first and second mold block portion is positioned, wherein said packaged semiconductor device being mounted on said electrically insulating substrate and said support plate through one of said at least one through-holes in said substrate, wherein the end portions of said electrode leads are placed on and are electrically connected to said conductor pattern on said second surface of said electrically insulating substrate, and an electrically conductive bonding material layer is provided between said exposed surface of said second portion of said heat sink block and said support plate, said bonding material layer having a thickness equal to or smaller that of said substrate.

Claim 7

An electronic device module comprising: a support plate; an electrically insulating substrate having a first metallized surface and a second surface provided with a conductor pattern, said substrate being placed on said support plate with said first metallized surface opposed to said support plate, at least one through-hole being formed in said substrate; and a packaged semiconductor device comprising: a semiconductor chip, a plurality of electrode leads, a plurality of connection conductors for interconnecting said semiconductor chip and said electrode leads, a heat sink blood attached to said chip and consisting of a first portion to which said second main surface of said semiconductor chip is attached and a second portion which extends from said first portion away from said semiconductor chip, and a mold block having a first mold block portion, which encloses said semiconductor chip, said plurality of electrode leads, said plurality of connection conductors and said first portion of said heat sink block, and a second mold block portion which encloses said second portion of said heat sink block, said second mold block portion being smaller than said first mold block portion and extending from said first mold block portion to form said mold block which has a "T"-shaped cross-section, with said first mold block portion forming a horizontal segment of "T", wherein said second portion of said heat sink block has an exposed surface which is not enclosed by said second mold block portion, and wherein each of said electrode leads has a free end surface portion that is positioned at a level farther away from said semiconductor chip than a level at which a boundary between said first and second mold block portion is positioned, wherein said packaged semiconductor device being mounted on said electrically insulating substrate and said support plate through one of said at least one through-holes in said substrate, wherein the end portions of said electrode leads are placed on and are electrically connected to said conductor pattern on said second surface of said electrically insulating substrate, and an electrically conductive bonding material layer is provided between said exposed surface of said second portion of said heat sink block and said support plate, said bonding material layer having a thickness equal to or smaller that of said substrate.

Claim 8

An electronic device module according to claim 5, wherein said second mold block portion has side faces which are tapered so that an intersection of the horizontal segment and a vertical segment in said "T"-shaped cross-section of said mold block is wider than its free end of said second mold block.

Claim 9

An electronic device module according to claim 5, wherein said conductor pattern on said second surface of said substrate includes strip line conductors, said semiconductor chip includes a high frequency power field effect transistor operable at a GHz frequency band and having source, drain and gate regions, and at least one of said plurality of electrode leads being electrically connected to said source, drain and gate regions, respectively, having a comb-like structure with a plurality of juxtaposed electrode leads electrically connected to one another so that each of said juxtaposed electrode leads serves to be connected with one of said strip line conductors for adjustment of impedance of the strip line conductor.