US5198760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method by which to detect direction of current flow in outputs of integrated circuits
Assignee: Raytheon Co
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Filing: 1991-09-30
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Granted: 1993-03-30
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Expires: 2011-09-30
Abstract
Abstract Test circuitry implemented in an integrated circuit having a plurality of outputs for testing the current at the outputs of output drivers of the integrated circuit without physical removal of the integrated circuit from an assembly in which it is incorporated. The test circuit includes a first test bus, a second test bus, and comparator circuitry responsive to the signals on the first and second test busses. Associated with each of the output drivers are (a) a current sensing resistor for sensing the current flow at the output of the buffer, (b) a first transmission gate connected between one side of the sensing resistor and the first test bus, and (c) a second transmission gate connected between the other side of the sensing resistor and the second test bus. The first and second transmission gates associated with an output buffer are controlled in parallel via a scan register. As to a selected output driver whose associated transmission gates are turned on, the comparison circuitry provides an indication as to whether the current flow sensed by a selected current sensing resistor is outside a predetermined range.
Inventors
- 👤 William D. Farwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318572; G01R19/00; G01R19/14; G01R31/316
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
93 words
A test circuit for an integrated circuit having output buffer for providing output signal on associated signal pad, comprising: a first test bus; a second test bus; current sensing means connected to said output buffers; selection means respectively associated with respective current sensing means for controllably coupling said current sensing means to said first and second test busses; and comparator means responsive to the signals on said first and second test busses for providing an indication of whether the current flow sensed by a selected current sensing means is outside a predetermined range.
Claim 2
Dependent Claim
93 words
A test circuit for an integrated circuit having output buffer for providing output signal on associated signal pad, comprising: a first test bus; a second test bus; current sensing means connected to said output buffers; selection means respectively associated with respective current sensing means for controllably coupling said current sensing means to said first and second test busses; and comparator means responsive to the signals on said first and second test busses for providing an indication of whether the current flow sensed by a selected current sensing means is outside a predetermined range.
Claim 3
Dependent Claim
83 words
The test circuit of claim 1 wherein: said current sensing means includes a current sensing resistor; said selection means includes (a) a first transmission gate connected between one side of said current sensing resistor and said first test bus, and (b) a second transmission gate connected between the other side of the associated current sensing resistor and said second test bus; and said comparator means includes first and second comparators having inputs connected to said first test bus and said second test bus.
Claim 4
Dependent Claim
25 words
The test circuit of claim 2 wherein the first and second transmission gates said an output buffer are controlled in parallel via a scan register.
Claim 5
Dependent Claim
121 words
A test circuit for an integrated circuit having an output buffer for providing output signal on an associated signal pad, comprising: a first test bus; a second test bus; current sensing means connected to said output buffer; selection means respectively associated with respective current sensing means for controllably coupling a selected current sensing means to said first and second test busses; and comparator means responsive to the signals on said first and second test busses for providing an indication of whether current in a first direction sensed by said current sensing means is greater than a first direction current limit, and whether current in a second direction sensed by said current sensing means is greater than a second direction current limit.
Claim 6
Dependent Claim
121 words
A test circuit for an integrated circuit having an output buffer for providing output signal on an associated signal pad, comprising: a first test bus; a second test bus; current sensing means connected to said output buffer; selection means respectively associated with respective current sensing means for controllably coupling a selected current sensing means to said first and second test busses; and comparator means responsive to the signals on said first and second test busses for providing an indication of whether current in a first direction sensed by said current sensing means is greater than a first direction current limit, and whether current in a second direction sensed by said current sensing means is greater than a second direction current limit.
Claim 7
Dependent Claim
75 words
A test circuit for an integrated circuit having output buffer for providing output signal on associated signal pads, comprising: current sensing means connected to said output buffer; comparator means selectively connectable to said current sensing means for providing an indication of whether current sensed by said current sensing means is outside a predetermined range; and selection means connected to said current sensing means for controllably connecting a selected current sensing means to said comparison means.
Claim 8
Dependent Claim
75 words
A test circuit for an integrated circuit having output buffer for providing output signal on associated signal pads, comprising: current sensing means connected to said output buffer; comparator means selectively connectable to said current sensing means for providing an indication of whether current sensed by said current sensing means is outside a predetermined range; and selection means connected to said current sensing means for controllably connecting a selected current sensing means to said comparison means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-29 | 1996-09-28 | 1997-03-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-29 | 2000-09-28 | 2001-03-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-29 | 2004-09-28 | 2005-03-30 | $7700.00 | Window Closed / Lapsed |