Capacitor-driven signal transmission circuit

Claim 2

A transmission line driver circuit, comprising: a signal input; a first discrete capacitor for storing a first voltage level corresponding to a first of two possible bit values of an input signal; a second discrete capacitor for storing a second voltage level corresponding to a second of said possible bit values of said input signal; a first voltage supply source selectively coupled to said first discrete capacitor for recharging said first discrete capacitor to said first voltage level; a second voltage supply source selectively coupled to said second discrete capacitor for recharging said second discrete capacitor to said second voltage level; a transmission line; and a switching circuit, an input of said switching circuit coupled to said signal input, an output of said switching circuit coupled to said transmission line, said first and second discrete capacitors coupled to said switching circuit, said switching circuit comprising an inverter coupled to said signal input and having an output, said inverter being operable to invert said input signal to produce an inverted signal on said inverter output having a bit value inverted from the bit value of said input signal, first and second discrete capacitor coupling switches, each having control nodes coupled to said output of said inverter, said first discrete capacitor coupling switch being operable to couple said discrete capacitor to said transmission line in response to a second bit value of said inverter signal on its switch control node, said second discrete capacitor coupling switch being operable to couple said second discrete capacitor to said transmission line in response to a first bit value of said inverted signal on its switch control node, said switching circuit being operable to couple said first discrete capacitor to said output in response to an input signal of a first bit value and being operable to couple said second discrete capacitor to said output in response to an input signal of said second bit value, such that the bit value received on said signal input is transmitted to said transmission line.

Claim 3

A circuit for transmitting a bivalent signal on a transmission line comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing on the last said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources; and a voltage stabilizer circuit for stabilizing the bit values transmitted on the transmission line, said voltage stabilizer circuit comprising a first and second stabilizer switches having respective control nodes coupled to said inverter output, said first stabilizer switch operable to couple a first stabilizing voltage supply source to said transmission line in response to receiving a second bit value of said inverter signal on its control node, said second stabilizer switch operable to couple a second stabilizing voltage source to said transmission line in response to receiving a first bit value of said inverter signal on its control node, said first and second stabilizing voltage supply sources each comprise a transistor having a control electrode and a current path, each said current path coupling a respective voltage source to a respective stabilizer switch, the control electrode of each said transistor coupled to a respective voltage source.

Claim 4

A circuit for transmitting a bivalent signal on a transmission line comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing on the last said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources; and a voltage stabilizer circuit for stabilizing the bit values transmitted on the transmission line, said voltage stabilizer circuit comprising a first and second stabilizer switches having respective control nodes coupled to said inverter output, said first stabilizer switch operable to couple a first stabilizing voltage supply source to said transmission line in response to receiving a second bit value of said inverter signal on its control node, said second stabilizer switch operable to couple a second stabilizing voltage source to said transmission line in response to receiving a first bit value of said inverter signal on its control node, said first and second stabilizing voltage supply sources each comprise a transistor having a control electrode and a current path, each said current path coupling a respective voltage source to a respective stabilizer switch, the control electrode of each said transistor coupled to a respective voltage source.

Claim 5

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources.

Claim 6

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources.

Claim 7

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing the last said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources, a first electrode of said first discrete capacitor being coupled to said first and third switches, a first electrode of said second discrete capacitor coupled to said second and fourth switches; a third discrete capacitor; and a second electrode of said first and second discrete capacitors being opposed to a respective first electrode coupled to ground through said third discrete capacitor to reduce AC coupling noise and a resistance coupled between said second electrodes of said first and second discrete capacitors on the one hand and ground on the other hand to stabilize the potential at said second electrodes.

Claim 8

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first switch having a control node coupled to said signal input, a first discrete capacitor, said first switch operable to couple said first voltage source to said first discrete capacitor responsive to a signal of said second bit value appearing on said control node; a second switch having a control node coupled to said signal input, a second discrete capacitor, said second switch operable to couple said second voltage source to said second discrete capacitor responsive to a signal of said first bit value appearing the last said control node; a transmission line node, a third switch having a control node coupled to said inverter output, said third switch operable to couple said first discrete capacitor to said transmission line node in response to said control node of said third switch receiving an inverter signal of said first bit value; a fourth switch having a control node coupled to said inverter output, said fourth switch operable to couple said second discrete capacitor to said transmission line node in response to said control node of said fourth switch receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said discrete capacitors is being recharged from a corresponding one of said voltage sources, a first electrode of said first discrete capacitor being coupled to said first and third switches, a first electrode of said second discrete capacitor coupled to said second and fourth switches; a third discrete capacitor; and a second electrode of said first and second discrete capacitors being opposed to a respective first electrode coupled to ground through said third discrete capacitor to reduce AC coupling noise and a resistance coupled between said second electrodes of said first and second discrete capacitors on the one hand and ground on the other hand to stabilize the potential at said second electrodes.

Claim 11

A transmission line driver circuit, comprising: a signal input; a first capacitor for storing a first voltage level corresponding to a first of two possible bit values of an input signal; a second capacitor for storing a second voltage level corresponding to a second of said possible bit values of said input signal; a first voltage supply source selectively coupled to said first capacitor for recharging said first discrete capacitor to said first voltage level; a second voltage supply source selectively coupled to said second capacitor for recharging said second discrete capacitor to said second voltage level; a transmission line; and a field effect transistor circuit, an input of said field effect transistor circuit coupled to said signal input, an output of said field effect transistor circuit coupled to said transmission line, said first and second capacitors coupled to said field effect transistor circuit, said field effect transistor circuit comprising an inverter coupled to said signal input and having an output, said inverter being operable to invert said input signal to produce an inverted signal on said inverter output having a bit value inverted from the bit value of said input signal, first and second capacitor coupling field effect transistors, each having control nodes coupled to said output of said inverter, said first capacitor coupling field effect transistor being operable to couple said capacitor to said transmission line in response to a second bit value of said inverter signal on its field effect transistor control node, said second capacitor coupling field effect transistor being operable to couple said second capacitor to said transmission line in response to a first bit value of said inverted signal on its switch control node, said switching circuit being operable to couple said first discrete capacitor to said output in response to an input signal of a first bit value and being operable to couple said second discrete capacitor to said output in response to an input signal of said second bit value, such that the bit value received on said signal input is transmitted to said transmission line.

Claim 12

A transmission line driver circuit, comprising: a signal input; a first capacitor for storing a first voltage level corresponding to a first of two possible bit values of an input signal; a second capacitor for storing a second voltage level corresponding to a second of said possible bit values of said input signal; a first voltage supply source selectively coupled to said first capacitor for recharging said first discrete capacitor to said first voltage level; a second voltage supply source selectively coupled to said second capacitor for recharging said second discrete capacitor to said second voltage level; a transmission line; and a field effect transistor circuit, an input of said field effect transistor circuit coupled to said signal input, an output of said field effect transistor circuit coupled to said transmission line, said first and second capacitors coupled to said field effect transistor circuit, said field effect transistor circuit comprising an inverter coupled to said signal input and having an output, said inverter being operable to invert said input signal to produce an inverted signal on said inverter output having a bit value inverted from the bit value of said input signal, first and second capacitor coupling field effect transistors, each having control nodes coupled to said output of said inverter, said first capacitor coupling field effect transistor being operable to couple said capacitor to said transmission line in response to a second bit value of said inverter signal on its field effect transistor control node, said second capacitor coupling field effect transistor being operable to couple said second capacitor to said transmission line in response to a first bit value of said inverted signal on its switch control node, said switching circuit being operable to couple said first discrete capacitor to said output in response to an input signal of a first bit value and being operable to couple said second discrete capacitor to said output in response to an input signal of said second bit value, such that the bit value received on said signal input is transmitted to said transmission line.

Claim 13

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources; and a voltage stabilizer circuit for stabilizing the bit value transmitted on the transmission line, said voltage stabilizer circuit comprising a first and second stabilizer field effect transistor having respective control nodes coupled to said inverter output, said first stabilizer field effect transistor operable to couple a first stabilizing voltage supply source to said transmission line in response to receiving a second bit value of said inverter signal on its control node, said second stabilizer field effect transistor operable to couple a second stabilizing voltage source to said transmission line in response to receiving a first bit value of said inverter signal on its control node, second stabilizing voltage supply sources each comprise a transistor having a control electrode and a current path, each said current path coupling a respective voltage source to a respective stabilizer field effect transistor, the control electrode of each said field effect transistor coupled to a respective voltage source.

Claim 14

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said discrete capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources; and a voltage stabilizer circuit for stabilizing the bit value transmitted on the transmission line, said voltage stabilizer circuit comprising a first and second stabilizer field effect transistor having respective control nodes coupled to said inverter output, said first stabilizer field effect transistor operable to couple a first stabilizing voltage supply source to said transmission line in response to receiving a second bit value of said inverter signal on its control node, said second stabilizer field effect transistor operable to couple a second stabilizing voltage source to said transmission line in response to receiving a first bit value of said inverter signal on its control node, second stabilizing voltage supply sources each comprise a transistor having a control electrode and a current path, each said current path coupling a respective voltage source to a respective stabilizer field effect transistor, the control electrode of each said field effect transistor coupled to a respective voltage source.

Claim 15

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources.

Claim 16

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving an input signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources.

Claim 17

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources, a first electrode of said first capacitor being coupled to said first and third field effect transistors, a first electrode of said second capacitor coupled to said second and fourth field effect transistors; a third capacitor; and a second electrode of said first and second capacitors being opposed to a respective first electrode coupled to ground through said third capacitor to reduce AC coupling noise and a resistance coupled between said second electrodes of said first and second capacitors on the one hand and ground on the other hand to stabilize the potential at said second electrodes.

Claim 18

A circuit for transmitting a bivalent signal on a transmission line, comprising: a signal input for receiving signal having one of two opposed bit values; an inverter coupled to said signal input and having an inverter output operable to output an inverted signal having a bit value opposite that of said input signal; a first voltage source for supplying a first voltage corresponding to a first of said bit values; a second voltage source for supplying a second voltage corresponding to a second of said bit values; a first field effect transistor having a control node coupled to said signal input, a first capacitor, said first field effect transistor operable to couple said first voltage source to said first capacitor responsive to a signal of said second bit value appearing on said control node; a second field effect transistor having a control node coupled to said signal input, a second capacitor, said second field effect transistor operable to couple said second voltage source to said second capacitor responsive to a signal of said first bit value appearing on said control node; a transmission line node, a third field effect transistor having a control node coupled to said inverter output, said third field effect transistor operable to couple said first capacitor to said transmission line node in response to said control node of said third field effect transistor receiving an inverter signal of said first bit value; a fourth field effect transistor having a control node coupled to said inverter output, said fourth field effect transistor operable to couple said second capacitor to said transmission line node in response to said control node of said fourth field effect transistor receiving an inverted signal of said second bit value, such that one of said capacitors transfers charge to said transmission line while the other of said capacitors is being recharged from a corresponding one of said voltage sources, a first electrode of said first capacitor being coupled to said first and third field effect transistors, a first electrode of said second capacitor coupled to said second and fourth field effect transistors; a third capacitor; and a second electrode of said first and second capacitors being opposed to a respective first electrode coupled to ground through said third capacitor to reduce AC coupling noise and a resistance coupled between said second electrodes of said first and second capacitors on the one hand and ground on the other hand to stabilize the potential at said second electrodes.