Patent US5196362A successfully refreshed from Google Patents.
US5196362A
Expired / Lapsed
US
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Multilayer wiring method of on-chip modification for an lsi
Assignee: Hitachi Ltd
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Filing: 1991-08-23
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Granted: 1993-03-23
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Expires: 2011-08-23
Abstract
Abstract In interconnecting signal wires between circuit elements of a semiconductor integrated circuit chip having a multilayered wiring structure, the signal wires are divided or classified into a first group of signal wires with lower modification-requisite possibilty and a second group of signal wires with higher modification-requisite possibility. The first group of signal wires are allocated to a lower wiring layer and wired therein. Then, the second group of signal wires are allocated to an upper wiring layer and wired therein. The second group of signal wires are allocated to and connected in the upper wiring layer, so that a laser is allowed to be fired directly to the upper wiring layer for disconnecting the signal wire or a laser CVD is allowed to be easily implemented on the upper wiring layer for connecting the signal wire, thereby enhancing reliability of modification. The first group of signal wires not to be modified are allocated to and connected in the lower wiring layer. Those signal wires not to be modified thus do not become any obstacle to the connecting area of the upper wiring layers, thereby allowing efficient use of the wiring channels.
Inventors
- 👤 Katsuyoshi Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 22:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43; H10W20/01; H10W20/031; H10W20/067; H10W20/068; H10W20/42
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
93 words
A multilayer wiring method for connecting signal wires between circuit elements included in a semiconductor integrated circuit chip having a plurality of wiring layers comprising the steps of: classifying said signal wires into a first group of signal wires with low modification-requisite possibility and a second group of signal wires with high modification-requisite possibility; allocating said first group of signal wires into at least one lower layer of said plurality of wiring layers; and allocating said second group of signal wires into at least one upper layer of said plurality of wiring layers.
Claim 2
Dependent Claim
93 words
A multilayer wiring method for connecting signal wires between circuit elements included in a semiconductor integrated circuit chip having a plurality of wiring layers comprising the steps of: classifying said signal wires into a first group of signal wires with low modification-requisite possibility and a second group of signal wires with high modification-requisite possibility; allocating said first group of signal wires into at least one lower layer of said plurality of wiring layers; and allocating said second group of signal wires into at least one upper layer of said plurality of wiring layers.
Claim 3
Dependent Claim
29 words
A multilayer wiring method according to claim 1, wherein said second group of signal wires are used as logical signal wires providing great allowance for a signal delay time.
Claim 4
Dependent Claim
130 words
A multilayer wiring method for interconnecting signal wires between cell terminals of circuit elements included in a semiconductor integrated circuit chip having two or more wiring layers, said layers being allocated in accordance with each type of signal wires, said multilayer wiring method comprising the steps of: dividing said signal wires into a first group of signal wires with low repair-requisite possibility and a second group of signal wires with high repair-requisite possibility; arranging cell terminals of said first group of signal wires and unused cell terminals in a lower layer of said two or more wiring layers to connect the wires; and leading cell terminals of said second group of signal wires out to an upper layer of said two or more wiring layers to interconnect the wires therein.
Claim 5
Dependent Claim
130 words
A multilayer wiring method for interconnecting signal wires between cell terminals of circuit elements included in a semiconductor integrated circuit chip having two or more wiring layers, said layers being allocated in accordance with each type of signal wires, said multilayer wiring method comprising the steps of: dividing said signal wires into a first group of signal wires with low repair-requisite possibility and a second group of signal wires with high repair-requisite possibility; arranging cell terminals of said first group of signal wires and unused cell terminals in a lower layer of said two or more wiring layers to connect the wires; and leading cell terminals of said second group of signal wires out to an upper layer of said two or more wiring layers to interconnect the wires therein.
Claim 6
Dependent Claim
63 words
A multilayer wiring method according to claim 3, wherein data of paths to be formed when the cell terminals of said second group of signal wires to the upper layer are led out to the upper layer are stored in a library and the lead-out wires for said cell terminals are formed of wiring patterns corresponding to the data stored in said library.
Claim 7
Dependent Claim
87 words
A multilayer wiring method according to claim 1, wherein the signal wires are categorized into three levels depending on the modification-requisite possibility thereof, signal wires of the most modification-requisite possibility are allocated into an upper layer of said plurality of wiring layers, signal wires of the least modification-requisite possibility are allocated to a lower layer of said plurality of wiring layers, and signal wires of intermediate-level modification-requisite possibility are allocated to the upper layers using idle wiring paths as modification-requisite possibility of the signal wires become higher.
Claim 8
Dependent Claim
43 words
A multilayer wiring method according to claim 1, wherein higher weights are applied to signals of a signal wire group with higher modification-requisite possibility and higher weighted signal wires are allocated to the upper layers when defining a connecting path or wiring layer.
Claim 9
Dependent Claim
44 words
A multilayer wiring method according to claim 6, wherein upper layers of said two or more wiring layers are allocated to the weighted signal wire groups in a wire connecting process in order to allocate the higher weighted signal wires to the upper layers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-22 | 1996-09-21 | 1997-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-22 | 2000-09-21 | 2001-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-22 | 2004-09-21 | 2005-03-23 | $7700.00 | Window Closed / Lapsed |