Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits

Claim 2

Integrated circuitry formed according to a method comprising the following steps: fabricating a semiconductor wafer to provide a pair of adjacent, substantially parallel and spaced word lines and to define regions for formation of stacked storage node capacitors and buried contacts therefor, the individual stacked capacitors overlapping the pair of adjacent word lines; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; providing an insulating layer to a first selected thickness atop the wafer and between the pair of word lines, the first selected thickness being greater than one-half the second separation distance to fill the second separation regions between the pair of word lines with insulating material, the first selected thickness being less than one-half the first separation distance to provide a space within the first separation regions between the pair of word lines, the space having a width; selectively removing portions of the insulating layer within the first separation regions to define buried contacts to underlying substrate; depositing a layer of conductive material to a second selected thickness atop the wafer and within the space; patterning the layer of conductive material to define lower storage node capacitor plates; and providing a capacitor dielectric and upper storage node capacitor plates above the lower storage node capacitor plates.

Claim 3

Integrated circuitry formed according to the method of claim 1 wherein the selected thickness is less than half the space width.

Claim 4

Integrated circuitry formed according to the method of claim 1 wherein the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material.

Claim 5

Integrated circuitry formed according to the method of claim 1 wherein the pair of word lines recited in claim 1 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 6

Integrated circuitry formed according to the method of claim 1 wherein the second selected thickness is less than half the space width, and the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material.

Claim 7

Integrated circuitry formed according to the method of claim 1 wherein the second selected thickness is less than half the space width, and the pair of word lines recited in claim 1 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 8

Integrated circuitry formed according to the method of claim 1 wherein the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material, and wherein the pair of word lines recited in claim 1 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 9

Integrated circuitry formed according to the method of claim 1 wherein the second selected thickness is less than half the space width; the method further comprising isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material, and wherein the pair of word lines recited in claim 1 define a first pair of word lines; and the method further comprising: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 10

Stacked capacitor memory integrated circuitry comprising: a pair of adjacent, substantially parallel and spaced word lines, the word lines having respective opposing outer edges and respective word line widths, respective word line width at given locations being defined by a straight line drawn normal to the opposing outer edges at the given locations, each word line of the pair having first and second regions of differing respective first and second widths alternating relative to one another along the substantially parallel and separated word lines; the first width being less than the second width; a series of stacked capacitors formed between and along the pair of word lines, the capacitors having individual lower capacitor plates which overlap the pair of word lines; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions substantially corresponding in longitudinal position along the pair with the word line first width regions, the second separation regions substantially corresponding in longitudinal position along the pair with the word line second width regions, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; an insulating material filling the second separation regions between the pair of word lines, buried contacts being provided to underlying substrate within the first separation regions; lower capacitor plates filling the buried contacts; and capacitor dielectric atop the lower capacitor plates and upper storage node capacitor plates atop the capacitor dielectric.

Claim 11

Stacked capacitor memory integrated circuitry comprising: a pair of adjacent, substantially parallel and spaced word lines, the word lines having respective opposing outer edges and respective word line widths, respective word line width at given locations being defined by a straight line drawn normal to the opposing outer edges at the given locations, each word line of the pair having first and second regions of differing respective first and second widths alternating relative to one another along the substantially parallel and separated word lines; the first width being less than the second width; a series of stacked capacitors formed between and along the pair of word lines, the capacitors having individual lower capacitor plates which overlap the pair of word lines; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions substantially corresponding in longitudinal position along the pair with the word line first width regions, the second separation regions substantially corresponding in longitudinal position along the pair with the word line second width regions, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; an insulating material filling the second separation regions between the pair of word lines, buried contacts being provided to underlying substrate within the first separation regions; lower capacitor plates filling the buried contacts; and capacitor dielectric atop the lower capacitor plates and upper storage node capacitor plates atop the capacitor dielectric.

Claim 12

The stacked capacitor memory integrated circuitry of claim 9 wherein the pair of word lines recited in claim 9 define a first pair of word lines; the stacked capacitor memory integrated circuitry further comprising: a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, an insulating material filling between the first and second word line pairs along locations of closest separation.

Claim 13

Integrated circuitry formed according to a method comprising the following steps: fabricating a semiconductor wafer to provide a pair of adjacent, substantially parallel and spaced word lines and to define regions for formation of stacked storage node capacitors and buried contacts therefor, the individual stacked capacitors overlapping the pair of adjacent word lines, the word lines having respective opposing outer edges and respective word line widths, respective word line width at given locations being defined by a straight line drawn normal to the opposing outer edges at the given locations, each word line of the pair having first and second regions of differing respective first and second widths alternating relative to one another along the substantially parallel and separated word lines; the first width being less than the second width; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions substantially corresponding in longitudinal position along the pair with the word line first width regions, the second separation regions substantially corresponding in longitudinal position along the pair with the word line second width regions, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; providing an insulating layer to a first selected thickness atop the wafer and between the pair of word lines, the first selected thickness being greater than one-half the second separation distance to fill the second separation regions between the pair of word lines with insulating material, the first selected thickness being less than one-half the first separation distance to provide a space within the first separation regions between the pair of word lines, the space having a width; selectively removing portions of the insulating layer within the first separation regions to define buried contacts to underlying substrate; depositing a layer of conductive material to a second selected thickness atop the wafer and within the space; patterning the layer of conductive material to define lower storage node capacitor plates; and providing a capacitor dielectric and upper storage node capacitor plates above the lower storage node capacitor plates.

Claim 14

Integrated circuitry formed according to a method comprising the following steps: fabricating a semiconductor wafer to provide a pair of adjacent, substantially parallel and spaced word lines and to define regions for formation of stacked storage node capacitors and buried contacts therefor, the individual stacked capacitors overlapping the pair of adjacent word lines, the word lines having respective opposing outer edges and respective word line widths, respective word line width at given locations being defined by a straight line drawn normal to the opposing outer edges at the given locations, each word line of the pair having first and second regions of differing respective first and second widths alternating relative to one another along the substantially parallel and separated word lines; the first width being less than the second width; the pair of adjacent word lines including first separation regions therebetween within which storage node capacitors and respective buried contacts are provided, the pair of adjacent word lines including second separation regions therebetween, the first and second separation regions alternating relative to one another between and along the substantially parallel and separated word lines, the first separation regions substantially corresponding in longitudinal position along the pair with the word line first width regions, the second separation regions substantially corresponding in longitudinal position along the pair with the word line second width regions, the first separation regions having a first separation distance which defines the spacing between the pair of word lines in the first separation regions, the second separation regions having a second separation distance which defines the spacing between the pair of word lines in the second separation regions, the second separation distance being less than the first separation distance; providing an insulating layer to a first selected thickness atop the wafer and between the pair of word lines, the first selected thickness being greater than one-half the second separation distance to fill the second separation regions between the pair of word lines with insulating material, the first selected thickness being less than one-half the first separation distance to provide a space within the first separation regions between the pair of word lines, the space having a width; selectively removing portions of the insulating layer within the first separation regions to define buried contacts to underlying substrate; depositing a layer of conductive material to a second selected thickness atop the wafer and within the space; patterning the layer of conductive material to define lower storage node capacitor plates; and providing a capacitor dielectric and upper storage node capacitor plates above the lower storage node capacitor plates.

Claim 15

Integrated circuitry formed according to the method of claim 11 wherein the selected thickness is less than half the space width.

Claim 16

Integrated circuitry formed according to the method of claim 11 wherein the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material.

Claim 17

Integrated circuitry formed according to the method of claim 11 wherein the pair of word lines recited in claim 11 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 18

Integrated circuitry formed according to the method of claim 11 wherein the second selected thickness is less than half the space width, and the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material.

Claim 19

Integrated circuitry formed according to the method of claim 11 wherein the second selected thickness is less than half the space width, and the pair of word lines recited in claim 11 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 20

Integrated circuitry formed according to the method of claim 11 wherein the method further comprises isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material, and wherein the pair of word lines recited in claim 11 define a first pair of word lines; and the method further comprises: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; and the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.

Claim 21

Integrated circuitry formed according to the method of claim 11 wherein the second selected thickness is less than half the space width; the method further comprising isotropically etching the insulating layer prior to buried contact etching to widen the space within the first separation region prior to deposition of the layer of conductive material, and wherein the pair of word lines recited in claim 11 define a first pair of word lines; and the method further comprising: fabricating the semiconductor wafer to provide a second pair of adjacent, substantially parallel and spaced word lines, the second pair of word lines being positioned adjacent the first pair of word lines, the second pair of word lines being mirror image in shape to the first pair of word lines; the first and second pairs of word lines including a closest separation distance, the closest separation distance being less than the first separation distance, the first selected thickness being greater than one-half the closest separation distance.