Methods and apparatus for maintaining cache integrity whenever a cpu write to rom operation is performed with rom mapped to ram

Claim 3

A method as set forth in claim 1 wherein said cache entry invalidation signal is provided to said CPU via said local bus.

Claim 4

A method as set forth in claim 1 further comprising the step of utilizing said CPU, in response to said invalidation signal, to invalidate any cache entry in said cache memory corresponding to a data entry located at a target address of said CPU write ROM operation.

Claim 5

A method as set forth in claim 1 further comprising the steps of: (a) placing a target address of said CPU write to ROM operation on said local bus; and (b) utilizing said CPU to invalidate any cache entry corresponding to the address on said local bus whenever said invalidation signal is provided to said CPU.

Claim 6

A method as set forth in claim 1 wherein said step of implementing a local memory controller snoop cycle further comprises the steps of: (a) determining if a memory write cycle has been initiated by said CPU; (b) determining if a ROM space address is on said local bus; and (c) determining if the cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 9

Apparatus for maintaining cache integrity in a computer system that includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), a local memory controller for controlling cooperation between said CPU, cache memory, RAM and ROM, and a local bus for interconnecting said local memory controller and said CPU, wherein said computer system is capable of supporting a cacheable ROM mapped to RAM mode of operation, comprising: (a) detection means, coupled to said CPU via said local bus, for detecting a CPU write to ROM operation when the cacheable ROM mapped to RAM mode of operation of said computer system is enabled; and (b) signalling means, coupled to said CPU via said local bus, responsive to the detection of a CPU write to ROM operation by said detection means, for providing a cache entry invalidation signal to said CPU whenever a CPU write to ROM operation occurs with ROM mapped to RAM space being cacheable.

Claim 10

Apparatus for maintaining cache integrity in a computer system that includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), a local memory controller for controlling cooperation between said CPU, cache memory, RAM and ROM, and a local bus for interconnecting said local memory controller and said CPU, wherein said computer system is capable of supporting a cacheable ROM mapped to RAM mode of operation, comprising: (a) detection means, coupled to said CPU via said local bus, for detecting a CPU write to ROM operation when the cacheable ROM mapped to RAM mode of operation of said computer system is enabled; and (b) signalling means, coupled to said CPU via said local bus, responsive to the detection of a CPU write to ROM operation by said detection means, for providing a cache entry invalidation signal to said CPU whenever a CPU write to ROM operation occurs with ROM mapped to RAM space being cacheable.

Claim 11

Apparatus as set forth in claim 7 wherein said CPU, in response to said cache entry invalidation signal, is operative to invalidate any cache entry in said cache memory corresponding to a data entry located at a target address of said CPU write to ROM operation.

Claim 12

Apparatus as set forth in claim 7 wherein said CPU is operative to place a target address of said CPU write to ROM operation on said local bus and invalidate any cache entry corresponding to an address on said local bus in response to said invalidation signal.

Claim 13

Apparatus as set forth in claim 7 wherein said detection means further comprises: (a) means for determining if a memory write cycle is in progress; (b) means for determining if a ROM space address is on said local bus; and (c) means for determining if the cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 14

A memory controller for maintaining cache data integrity in a computer system that includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), and a local bus for interconnecting said memory controller and said CPU, wherein said computer system is capable of supporting a plurality of operating modes including a cacheable ROM mapped to RAM mode of operation, comprising: (a) memory write cycle detection means, coupled to said local bus, for determining if a memory write cycle has been initiated by said CPU; (b) ROM address space detection means, coupled to said local bus, for determining if a ROM space address is on said local bus; (c) mode determination means for determining if the cacheable ROM mapped to RAM mode of operating said system is enabled; and (d) means for providing a cache entry invalidation signal to said CPU whenever said memory controller determines that a memory write cycle has been initiated with an address on said local bus being in ROM address space while said cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 15

A memory controller for maintaining cache data integrity in a computer system that includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), and a local bus for interconnecting said memory controller and said CPU, wherein said computer system is capable of supporting a plurality of operating modes including a cacheable ROM mapped to RAM mode of operation, comprising: (a) memory write cycle detection means, coupled to said local bus, for determining if a memory write cycle has been initiated by said CPU; (b) ROM address space detection means, coupled to said local bus, for determining if a ROM space address is on said local bus; (c) mode determination means for determining if the cacheable ROM mapped to RAM mode of operating said system is enabled; and (d) means for providing a cache entry invalidation signal to said CPU whenever said memory controller determines that a memory write cycle has been initiated with an address on said local bus being in ROM address space while said cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 16

A memory controller as set forth in claim 11 further comprising storage means for storing at least one mode enabled bit for indicating which of said plurality of operating modes of said computer system is enabled.

Claim 17

A computer system, including cache memory that supports a cacheable ROM mapped to RAM mode of operation and maintains cache integrity whenever a CPU write to ROM operation is performed with said cacheable ROM mapped to RAM mode being enabled, comprising: (a) a central processing unit (CPU); (b) a cache memory associated with said CPU; (c) a Random Access Memory (RAM); (d) a Read Only Memory (ROM; (e) a local memory controller for controlling cooperation between said CPU, said cache memory, said RAM and said ROM; (f) a local bus for interconnecting said local memory controller and said CPU; (g) detection means, coupled to said CPU via said local bus, for detecting a CPU write to ROM operation when the cacheable ROM mapped to RAM mode of operation of said computer system is enabled; and (h) signalling means, coupled to said CPU via said local bus, responsive to the detection of a CPU write to ROM operation by said detection means, for providing a cache entry invalidation signal to said CPU whenever a CPU write to ROM operation occurs with ROM mapped to RAM space being cacheable.

Claim 18

A computer system, including cache memory that supports a cacheable ROM mapped to RAM mode of operation and maintains cache integrity whenever a CPU write to ROM operation is performed with said cacheable ROM mapped to RAM mode being enabled, comprising: (a) a central processing unit (CPU); (b) a cache memory associated with said CPU; (c) a Random Access Memory (RAM); (d) a Read Only Memory (ROM; (e) a local memory controller for controlling cooperation between said CPU, said cache memory, said RAM and said ROM; (f) a local bus for interconnecting said local memory controller and said CPU; (g) detection means, coupled to said CPU via said local bus, for detecting a CPU write to ROM operation when the cacheable ROM mapped to RAM mode of operation of said computer system is enabled; and (h) signalling means, coupled to said CPU via said local bus, responsive to the detection of a CPU write to ROM operation by said detection means, for providing a cache entry invalidation signal to said CPU whenever a CPU write to ROM operation occurs with ROM mapped to RAM space being cacheable.

Claim 19

A computer system as set forth in claim 13 wherein said CPU, in response to said cache entry invalidation signal, is operative to invalidate any cache entry in said cache memory corresponding to a data entry located at a target address of said CPU write to ROM operation.

Claim 20

A computer system as set forth in claim 13 wherein said CPU is operative to place a target address of said CPU write to ROM operation on said local bus and invalidate any cache entry corresponding to an address on said local bus in response to said invalidation signal.

Claim 21

A computer system as set forth in claim 13 wherein said detection means further comprises: (a) means for determining if a memory write cycle is in progress; (b) means for determining if a ROM space address is on said local bus; and (c) means for determining if the cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 22

A computer system including a memory controller for maintaining cache data integrity, wherein said system includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), and a local bus for interconnecting said memory controller and said CPU, and further wherein said computer system is capable of supporting a cacheable ROM mapped to RAM mode of operation, comprising: (a) memory write cycle detection means for determining if a memory write cycle has been initiated by said CPU; (b) ROM space address detection means for determining if a ROM space address is on said local bus; (c) mode determination means for determining if the cacheable ROM mapped to RAM mode of operating said computer system is enabled; and (d) means for providing a cache entry invalidation signal to said CPU whenever a memory write cycle has been initiated with a ROM space address on said local bus while said cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 23

A computer system including a memory controller for maintaining cache data integrity, wherein said system includes a central processing unit (CPU), cache memory associated with said CPU, Random Access Memory (RAM), Read Only Memory (ROM), and a local bus for interconnecting said memory controller and said CPU, and further wherein said computer system is capable of supporting a cacheable ROM mapped to RAM mode of operation, comprising: (a) memory write cycle detection means for determining if a memory write cycle has been initiated by said CPU; (b) ROM space address detection means for determining if a ROM space address is on said local bus; (c) mode determination means for determining if the cacheable ROM mapped to RAM mode of operating said computer system is enabled; and (d) means for providing a cache entry invalidation signal to said CPU whenever a memory write cycle has been initiated with a ROM space address on said local bus while said cacheable ROM mapped to RAM mode of operating said computer system is enabled.

Claim 24

A computer system as set forth in claim 17 wherein said memory write cycle detection means, said ROM space address detection means, said mode determination means and said means for providing a cache entry invalidation signal, are all incorporated in said memory controller.