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Cache-memory architecture comprising a single address tag for each cache memory
Assignee: Nortel Networks Ltd
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Filing: 1992-04-20
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Granted: 1993-03-09
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Expires: 2012-04-20
Abstract
Abstract A cache-memory system comprising a processor bus for communicating between an associated processor (CPU) and associated cache-memory management units (CMMUs) communicating through the processor bus and each having a single cache address tag for addressing one associated cache; and each one of the plurality of CMMUs communicating through an associated one of a plurality of memory buses with a main memory of the system.
Inventors
- 👤 Victor J. Menasce
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 14:08
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
120 words
A cache-memory system comprising: a central processing unit (CPU); a plurality of cache-memory management units (CMMUs), each of said CMMUs having a single cache address tag for addressing one associated cache; a processor bus for providing communication between said CPU and said CMMUs; a plurality of main-memory storage units; and a plurality of buses for providing communication between said CMMUs and said main-memory storage units, each of said memory buses being associated with only one of said CMMUs and with only one of said main-memory storage units, such that each word stored in one of said CMMUs is associated with only one word stored in one of said main-memory storage units, thereby increasing memory bandwidth while decreasing average memory latency.
Claim 2
Dependent Claim
120 words
A cache-memory system comprising: a central processing unit (CPU); a plurality of cache-memory management units (CMMUs), each of said CMMUs having a single cache address tag for addressing one associated cache; a processor bus for providing communication between said CPU and said CMMUs; a plurality of main-memory storage units; and a plurality of buses for providing communication between said CMMUs and said main-memory storage units, each of said memory buses being associated with only one of said CMMUs and with only one of said main-memory storage units, such that each word stored in one of said CMMUs is associated with only one word stored in one of said main-memory storage units, thereby increasing memory bandwidth while decreasing average memory latency.
Claim 3
Dependent Claim
20 words
The cache-memory system of claim 1, wherein each one of said plurality of caches comprises only one word per line.
Claim 4
Dependent Claim
29 words
The cache memory system of claims 1 or 2, wherein each cache array has an effective number of words/line which is larger than its actual number of words/line stored.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-03-08 | 1996-09-07 | 1997-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-03-08 | 2000-09-07 | 2001-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-03-08 | 2004-09-07 | 2005-03-09 | $7700.00 | Window Closed / Lapsed |