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Patent US5188972A successfully refreshed from Google Patents.
US5188972A
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Method for making bipolar transistor by self-aligning the emitter to the base contact diffusion
Assignee: Microsemi Storage Solutions Inc
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Filing: 1992-04-28
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Granted: 1993-02-23
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Expires: 2012-04-28
Abstract
Abstract A semiconductor structure having a high precision analog polysilicon capacitor with a self-aligned extrinsic base region of a bipolar transistor is disclosed. The structure is formed by simultaneously forming the dielectric layer of the capacitor with the formation of the base region of the bipolar transistor. A final oxidation step in the formation of the capacitor causes the base region to diffuse to form a self-aligned extrinsic base diffusion region.
Inventors
- 👤 Ying K. Shum
- 👤 Sik K. Lui
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:15
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D10/00; H10D10/01; H10D10/051; H10D88/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
49 words
An improved method for making a semiconductor structure, wherein the structure has a bipolar transistor portion with a self-aligned extrinsic base, and a capacitor portion having a pair of polysilicon electrodes separated by a dielectric region, the improvement comprising forming the self-aligned extrinsic base simultaneously with the dielectric region.
Claim 2
Dependent Claim
49 words
An improved method for making a semiconductor structure, wherein the structure has a bipolar transistor portion with a self-aligned extrinsic base, and a capacitor portion having a pair of polysilicon electrodes separated by a dielectric region, the improvement comprising forming the self-aligned extrinsic base simultaneously with the dielectric region.
Claim 3
Independent Claim
178 words
A method for making a semiconductor structure on a semiconductive substrate having a field oxide region and a buffer oxide region thereon, the structure having a bipolar transistor portion with a self-aligned extrinsic base and a capacitor portion having a pair of polysilicon electrodes separated by a silicon dioxide-silicon nitride-silicon dioxide dielectric region, said method comprising: a. depositing a first layer of polysilicon on a portion of the field oxide region, forming a first polysilicon electrode; b. oxidizing the first polysilicon electrode; c. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; d. masking an extrinsic base region over a portion of the buffer oxide region; e. etching the silicon nitride layer to form an opening in the nitride layer above the portion of the buffer oxide region; f. implanting a dopant material through the window to form the extrinsic base; g. oxidizing the nitride layer while simultaneously diffusing the dopant material in said base; and h. depositing a second layer of polysilicon on the oxidized nitride layer, forming the second polysilicon electrode.
Claim 4
Independent Claim
178 words
A method for making a semiconductor structure on a semiconductive substrate having a field oxide region and a buffer oxide region thereon, the structure having a bipolar transistor portion with a self-aligned extrinsic base and a capacitor portion having a pair of polysilicon electrodes separated by a silicon dioxide-silicon nitride-silicon dioxide dielectric region, said method comprising: a. depositing a first layer of polysilicon on a portion of the field oxide region, forming a first polysilicon electrode; b. oxidizing the first polysilicon electrode; c. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; d. masking an extrinsic base region over a portion of the buffer oxide region; e. etching the silicon nitride layer to form an opening in the nitride layer above the portion of the buffer oxide region; f. implanting a dopant material through the window to form the extrinsic base; g. oxidizing the nitride layer while simultaneously diffusing the dopant material in said base; and h. depositing a second layer of polysilicon on the oxidized nitride layer, forming the second polysilicon electrode.
Claim 5
Independent Claim
125 words
A method for making a semiconductor structure, comprising: a. forming a field oxide region and a buffer oxide region on a silicon substrate; b. forming a first capacitor electrode on a portion of the field oxide region; c. forming an insulating dielectric region over the first electrode to isolate the first electrode; d. forming a self-aligned extrinsic base region of a bipolar transistor in a first portion of the silicon substrate simultaneously with the formation of the insulating dielectric region; e. forming a second capacitor electrode over the dielectric region; f. forming an emitter region of said bipolar transistor in a second portion of the silicon substrate; and g. forming a collector region of said bipolar transistor in a third portion of the silicon substrate.
Claim 6
Independent Claim
125 words
A method for making a semiconductor structure, comprising: a. forming a field oxide region and a buffer oxide region on a silicon substrate; b. forming a first capacitor electrode on a portion of the field oxide region; c. forming an insulating dielectric region over the first electrode to isolate the first electrode; d. forming a self-aligned extrinsic base region of a bipolar transistor in a first portion of the silicon substrate simultaneously with the formation of the insulating dielectric region; e. forming a second capacitor electrode over the dielectric region; f. forming an emitter region of said bipolar transistor in a second portion of the silicon substrate; and g. forming a collector region of said bipolar transistor in a third portion of the silicon substrate.
Claim 7
Dependent Claim
49 words
A method according to claim 3, wherein the step of forming a first capacitor electrode comprises: a. depositing polysilicon at high temperature on a first area of the field oxide region; b. doping the polysilicon with an n-type material; and c. patterning the polysilicon to form the first electrode.
Claim 8
Dependent Claim
102 words
A method according to claim 4, wherein the simultaneous steps of forming an insulating dielectric region and forming an extrinsic base region comprise: a. oxidizing the first polysilicon electrode; b. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; c. masking an extrinsic base region over the first portion of the silicon substrate; d. etching the nitride layer to form a window in the nitride layer above the first portion of silicon substrate; e. implanting a dopant material through the window; and f. oxidizing the nitride layer while simultaneously diffusing the dopant to form the extrinsic base.
Claim 9
Dependent Claim
119 words
A method according to claim 4, wherein the simultaneous steps of forming an insulating dielectric region and forming an extrinsic base region comprise: a. oxidizing the first polysilicon electrode; b. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; c. oxidizing the nitride layer; d. masking the structure to form a window over a portion of the buffer oxide region; e. implanting a dopant material through the window to form the base region; and f. masking the structure to form simultaneously a dielectric region over the first polysilicon electrode and a region above the portion over the buffer oxide region to expose the substrate to a base contact diffusion region and an emitter region.
Claim 10
Independent Claim
189 words
A method for making a semiconductor structure on a semiconductive substrate having a field oxide region and a buffer oxide region thereon, the structure having a bipolar transistor portion with a self-aligned extrinsic base and a capacitor portion having a pair of polysilicon electrodes separated by a silicon dioxide-silicon nitride-silicon dioxide dielectric region, said method comprising: a. depositing a first layer of polysilicon on a portion of the field oxide region, forming a first polysilicon electrode; b. oxidizing the first polysilicon electrode; c. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; d. oxidizing the nitride layer; e. masking the structure to form a window over a portion of the buffer oxide region; f. implanting a dopant material through the window to form the base region; g. masking the structure to form simultaneously a dielectric region over the first polysilicon electrode and a region above the portion over the buffer oxide region to expose the substrate to a base contact diffusion region and an emitter region; and h. depositing a second layer of polysilicon on the oxidized nitride layer, forming the second polysilicon electrode.
Claim 11
Independent Claim
189 words
A method for making a semiconductor structure on a semiconductive substrate having a field oxide region and a buffer oxide region thereon, the structure having a bipolar transistor portion with a self-aligned extrinsic base and a capacitor portion having a pair of polysilicon electrodes separated by a silicon dioxide-silicon nitride-silicon dioxide dielectric region, said method comprising: a. depositing a first layer of polysilicon on a portion of the field oxide region, forming a first polysilicon electrode; b. oxidizing the first polysilicon electrode; c. depositing a silicon nitride layer over the oxidized polysilicon and the buffer oxide region; d. oxidizing the nitride layer; e. masking the structure to form a window over a portion of the buffer oxide region; f. implanting a dopant material through the window to form the base region; g. masking the structure to form simultaneously a dielectric region over the first polysilicon electrode and a region above the portion over the buffer oxide region to expose the substrate to a base contact diffusion region and an emitter region; and h. depositing a second layer of polysilicon on the oxidized nitride layer, forming the second polysilicon electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-02-23 | 1996-08-24 | 1997-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-02-23 | 2000-08-24 | 2001-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-02-23 | 2004-08-24 | 2005-02-23 | $7700.00 | Window Closed / Lapsed |