Reference voltage generator for dynamic random access memory

Claim 1

A reference voltage generator comprising: first, second and third FETs of a first channel type, each having a gate, a drain and a source; fourth, fifth and sixth FETs of a second channel type opposite to said first channel type, each having a gate, a drain and a source; a first resistance element connected between a first voltage terminal and the gate and drain of said first FET; a second resistance element connected between a second voltage terminal and the gate and drain of said fourth FET; a third resistance element connected between the first voltage terminal and the drain of said second FET; and a fourth resistance element connected between the second voltage terminal and the drain of said fifth FET, in which: the sources of both first and fourth FETs are connected to each other; the gates of said second and fifth FETs are connected to the gates of said first and fourth FETs, respectively; the gates of said third and sixth FETs are connected to the drains of said fifth and second FETs, respectively; the sources of said third and sixth FETs are connected to the second voltage terminal, respectively; the sources of said second and fifth FETs and the drains of said sixth and third FETs are connected to a reference voltage output terminal; and the resistance values of said third and fourth resistance elements are selected so that said sixth and third FETs are essentially non-conductive under balanced conditions.