Method and apparatus for testing an analog to digital converter

Claim 2

Test apparatus for testing circuitry in an analog to digital converter (ADC) which has a plurality of resistors connected in series to form a resistor array with a first end and a second end, the test apparatus comprising: first logic means coupled to the first end of the resistor array, for applying an analog voltage level to the first end of the resistor array when the ADC is not in a special test mode, and for applying a first digital voltage level to the first end of the resistor array when the ADC is in the special test mode; second logic means coupled to at least two of the plurality of resistors for selectively coupling a portion of the resistor array to an output signal having a second voltage level which is analog when the ADC is not in the special test mode and which is digital when the ADC is in the special test mode; and third logic means used only in the special test mode, coupled to the second logic means and the first end of the resistor array, for comparing the first voltage level of the first end of the resistor array to the second voltage level of the output signal for producing a comparison result.

Claim 3

The test apparatus according to claim 1, further comprising: a storage means for receiving and storing a digital value that determines which of the plurality of resistors will be included in the portion of the resistor array that is coupled to the output signal by the second logic means.

Claim 4

The test apparatus according to claim 2 wherein the storage means receives the digital value from a source external to the analog to digital converter (ADC) only when the ADC is in the special test mode.

Claim 5

The test apparatus according to claim 2, further comprising: a transferring means coupled to the storage means and the second logic means for transferring the digital value from the storage means to the second logic means.

Claim 6

The test apparatus according to claim 2, further comprising: a decoding means coupled to the storage means and the second logic means for decoding the digital value.

Claim 7

The test apparatus according to claim 1 wherein the analog to digital converter (ADC) is located on a semiconductor chip and the test apparatus is also located on that same semiconductor chip.

Claim 8

The test apparatus according to claim 1, further comprising: a control means coupled to the third logic means for enabling the third logic means to compare the first voltage level to the second voltage level.

Claim 9

The test apparatus according to claim 7, wherein the control means enables the third logic means only when the analog to digital converter (ADC) is in the special test mode.

Claim 10

The test apparatus according to claim 1, further comprising: fourth logic means coupled to the third logic means for transmitting the comparision result outside of the analog to digital converter (ADC).

Claim 11

The test apparatus according to claim 1 wherein the third logic means determines, based upon the comparison result, whether there is a conductive path from the first end of the resistor array to the output signal.

Claim 12

The test apparatus according to claim 1 wherein the third logic means uses an exclusive-OR function.

Claim 15

The method according to claim 12 further comprising the step of: determining, based upon the comparison result, whether there is a conductive path from the first end of the resistor array to the output signal.

Claim 16

The method according to claim 12 wherein the step of using the value to determine which portion of the resistor array to couple to an output signal further comprises the step of: decoding the value.

Claim 17

The method according to claim 12 further comprising the step of: using a control signal to enable comparison of the first digital voltage level to the second digital voltage level.

Claim 18

The method according to claim 15 wherein the step of using a control signal to enable comparison of the first digital voltage level to the second digital voltage level is only performed when the analog to digital converter (ADC) is in the special test mode.

Claim 19

The method according to claim 12 further comprising the step of: transferring the comparison result outside of the analog to digital converter (ADC).

Claim 20

The method according to claim 12 wherein the step of comparing the first digital voltage level to the second digital voltage level further comprises the step of: using an exclusive-OR function.

Claim 21

Test apparatus for testing circuitry in an analog to digital converter (ADC) which has a plurality of resistors connected in series to form a resistor array with a first end and a second end, the test apparatus comprising: first logic means coupled to the first end of the resistor array, for applying an analog voltage level to the first end of the resistor array when the ADC is not in a special test mode, and for applying a first digital voltage level to the first end of the resistor array when the ADC is in the special test mode; second logic means coupled to at least two of the plurality of resistors for selectively coupling a portion of the resistor array to an output signal having a second voltage level which is analog when the ADC is not in the special test mode and which is digital when the ADC is in the special test mode; third logic means used only in the special test mode, coupled to the second logic means and the first end of the resistor array, for comparing the first voltage level of the first end of the resistor array to the second voltage level of the output signal for producing a comparison result; fourth logic means coupled to the third logic means for transmitting the comparison result outside of the analog to digital converter (ADC); a storage means for receiving and storing a digital value that determines which of the plurality of resistors will be included in the portion of the resistor array that is coupled to the output signal by the second logic means; and a control means coupled to the third logic means for enabling the third logic means to compare the first voltage level to the second voltage level.

Claim 22

Test apparatus for testing circuitry in an analog to digital converter (ADC) which has a plurality of resistors connected in series to form a resistor array with a first end and a second end, the test apparatus comprising: first logic means coupled to the first end of the resistor array, for applying an analog voltage level to the first end of the resistor array when the ADC is not in a special test mode, and for applying a first digital voltage level to the first end of the resistor array when the ADC is in the special test mode; second logic means coupled to at least two of the plurality of resistors for selectively coupling a portion of the resistor array to an output signal having a second voltage level which is analog when the ADC is not in the special test mode and which is digital when the ADC is in the special test mode; third logic means used only in the special test mode, coupled to the second logic means and the first end of the resistor array, for comparing the first voltage level of the first end of the resistor array to the second voltage level of the output signal for producing a comparison result; fourth logic means coupled to the third logic means for transmitting the comparison result outside of the analog to digital converter (ADC); a storage means for receiving and storing a digital value that determines which of the plurality of resistors will be included in the portion of the resistor array that is coupled to the output signal by the second logic means; and a control means coupled to the third logic means for enabling the third logic means to compare the first voltage level to the second voltage level.

Claim 23

The test apparatus according to claim 19, wherein the control means enables the third logic means only when the analog to digital converter (ADC) is in the special test mode.