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US5185285A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of producing polycrystalline silicon resistor

Assignee: Seiko Instruments Inc
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Filing: 1991-05-30
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Granted: 1993-02-09
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Expires: 2011-05-30
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Abstract

Abstract A metal film and a polysilicon film are formed in one wiring, in that after a first polysilicon film is formed, an insulating film is formed on a region where a high-resistance portion of the polysilicon film is to be formed and, then, a metal film is deposited thereon. Then, the metal film deposited on the insulating film is removed. Thereafter, the wiring is formed by photolithography.

Inventors

  • 👤 Takashi Hasaka

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 13:07
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; Y; Y10; Y10S; Y10S148/00; Y10S148/136

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 226 words
A method of producing semiconductor device element including a polycrystalline silicon film resistor, comprising the steps of: forming a first insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the first insulating film, the polycrystalline silicon film having a selected region containing a resistor-forming part and a conductor lead-forming part contiguous with the resistor-forming part; doping the selected region of the polycrystalline silicon film with impurities in an amount to cause the selected region to have a high electrical resistivity; covering the doped selected region with a second insulating film; pattern in the second insulating film by removing a part of the second insulating film which covers the conductor lead-forming part; heavily doping parts of the selected region of the polycrystalline silicon film which are not covered by the patterned second insulating film with impurities selected to cause those film parts to have an electrical resistively which is substantially lower than that of the part of the selected region which is covered with the patterned second insulating film; forming a metal film on the heavily doped polycrystalline silicon polysilicon film parts and on the patterned second insulating film; selectively removing a part of the metal film from above a part of the patterned second insulating film; and selectively patterning parts of the polycrystalline silicon film, the metal film and the second insulating film.
Claim 2
Independent Claim 226 words
A method of producing semiconductor device element including a polycrystalline silicon film resistor, comprising the steps of: forming a first insulating film on a semiconductor substrate; forming a polycrystalline silicon film on the first insulating film, the polycrystalline silicon film having a selected region containing a resistor-forming part and a conductor lead-forming part contiguous with the resistor-forming part; doping the selected region of the polycrystalline silicon film with impurities in an amount to cause the selected region to have a high electrical resistivity; covering the doped selected region with a second insulating film; pattern in the second insulating film by removing a part of the second insulating film which covers the conductor lead-forming part; heavily doping parts of the selected region of the polycrystalline silicon film which are not covered by the patterned second insulating film with impurities selected to cause those film parts to have an electrical resistively which is substantially lower than that of the part of the selected region which is covered with the patterned second insulating film; forming a metal film on the heavily doped polycrystalline silicon polysilicon film parts and on the patterned second insulating film; selectively removing a part of the metal film from above a part of the patterned second insulating film; and selectively patterning parts of the polycrystalline silicon film, the metal film and the second insulating film.

References Cited (Backward Citations)

US4643777A Cited
US4604789A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-02-09 1996-08-10 1997-02-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-02-09 2000-08-10 2001-02-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-02-09 2004-08-10 2005-02-09 $7700.00 Window Closed / Lapsed

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