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US5185279A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing insulated-gate type field effect transistor

Assignee: Toshiba Corp
•
Filing: 1991-03-22
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Granted: 1993-02-09
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Expires: 2011-03-22
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Abstract

Abstract A method of manufacturing an insulated-gate type field effect transistor includes the steps of forming an insulating film, on a semiconductor substrate, forming a first polycrystalline silicon layer on the insulating film, forming a second polycrystalline silicon layer on the frist polycrystalline silicon layer, patterning the first and second polycrystalline silicon layers to form a gate electrode and a masking layer, doping an impurity of a first conductivity type in the semiconductor substrate using the gate electrode and the masking layer as masks, thereby forming a source region and a drain region, starting etching the masking layer, detecting a natural oxide film on the gate electrode, stopping the etching, and ion-implanting an impurity of a second conductivity type in a region of the semiconductor substrate under the gate electrode through the gate electrode, thereby forming a channel-doped region. In this method, after the source and drain regions are formed, the impurity of the second conductivity type is ion-implanted in the substrate through the thin gate electrode to form the channel-doped region.

Inventors

  • 👤 Yukihiro Ushiku

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; Y; Y10; Y10S; Y10S148/00; Y10S148/082

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 155 words
A method of manufacturing an insulated-gate type field effect transistor, comprising the steps of: forming an insulating film, on a semiconductor substrate; forming a first polycrystalline silicon layer on said insulating film; forming a natural oxide film on said first polycrystalline layer; forming a second polycrystalline silicon layer on said natural oxide film; patterning said first polycrystalline silicon layers, said natural oxide film, and said second polycrystalline silicon layers to form a gate electrode and a masking layer; doping an impurity of a first conductivity type in said semiconductor substrate using said gate electrode and said masking layer as masks, thereby forming a source region and a drain region; starting etching said masking layer; detecting said natural oxide film on said gate electrode; stopping the etching; and ion-implanting an impurity of a second conductivity type in a region of said semiconductor substrate under said gate electrode through said gate electrode, thereby forming a channel-doped region.
Claim 2
Independent Claim 155 words
A method of manufacturing an insulated-gate type field effect transistor, comprising the steps of: forming an insulating film, on a semiconductor substrate; forming a first polycrystalline silicon layer on said insulating film; forming a natural oxide film on said first polycrystalline layer; forming a second polycrystalline silicon layer on said natural oxide film; patterning said first polycrystalline silicon layers, said natural oxide film, and said second polycrystalline silicon layers to form a gate electrode and a masking layer; doping an impurity of a first conductivity type in said semiconductor substrate using said gate electrode and said masking layer as masks, thereby forming a source region and a drain region; starting etching said masking layer; detecting said natural oxide film on said gate electrode; stopping the etching; and ion-implanting an impurity of a second conductivity type in a region of said semiconductor substrate under said gate electrode through said gate electrode, thereby forming a channel-doped region.
Claim 3
Dependent Claim 40 words
A method according to claim 1, wherein said etching of said masking layer is performed in a plasma atmosphere, and said detecting of the natural oxide film on said gate electrode is performed by measuring a potential of the plasma.
Claim 4
Dependent Claim 18 words
A method according to claim 1, wherein a thickness of said gate electrode is 500 to 2500 Å.

References Cited (Backward Citations)

JPS58184768A Cited
US4590665A Cited
US4683637A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-02-09 1996-08-10 1997-02-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-02-09 2000-08-10 2001-02-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-02-09 2004-08-10 2005-02-09 $7700.00 Window Closed / Lapsed

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