Self-aligned, self-passivated advanced dual lift-off heterojunction bipolar transistor method

Claim 2

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; forming a photoresist mask out of the photoresist, characterized by an emitter region pedestal surrounded by an emitter peripheral region and a base contact region, by etching the photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and a contact to the emitter.

Claim 3

The process of claim 1, comprising the further steps of: etching an opening through said insulation, and through the collector layer to the subcollector layer for said contact to the subcollector; depositing collector contact metal in said opening; and, isolating the contact metal.

Claim 4

The process of claim 2, comprising the further steps of: establishing an opening through said insulation to the collector layer; and, depositing Schottky contact material in said opening to form a diode using the subcollector contact of said transistor as the second contact for the diode.

Claim 5

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; forming a photoresist mask out of the photoresist, characterized by an emitter region pedestal surrounded by an emitter peripheral region and a base contact region, by etching the photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and to the said other cap layer for the emitter.

Claim 6

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; forming a photoresist mask out of the photoresist, characterized by an emitter region pedestal surrounded by an emitter peripheral region and a base contact region, by etching the photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and to the said other cap layer for the emitter.

Claim 7

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; forming a photoresist mask out of the further photoresist, characterized by an emitter region pedestal surrounded by an emitter peripheral region and a base contact region, by etching the photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and to the pedestal layer of said other cap layer for the emitter.

Claim 8

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; forming a photoresist mask out of the further photoresist, characterized by an emitter region pedestal surrounded by an emitter peripheral region and a base contact region, by etching the photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and to the pedestal layer of said other cap layer for the emitter.

Claim 9

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; delineating an emitter contact location; depositing a further layer of photoresist over the mesa; forming a photoresist mask out of the further photoresist, characterized by an emitter region pedestal including an emitter contact, surrounded by an emitter peripheral region and a base contact region, by etching the further photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and a contact to the emitter in said emitter contact location.

Claim 10

A self-aligned and self-passivated heterojunction bipolar transistor process, comprising the steps of: forming a semiconductor wafer including an undoped substrate, an N+ gallium arsenide subcollector layer over the substrate, a gallium arsenide collector layer doped one type over the subcollector, a gallium arsenide base layer doped a different type from said one type over the collector layer, an aluminum gallium arsenide emitter layer doped said one type over the base layer, and a pair of cap layers, one over the emitter layer and the other over the one cap layer; forming a mesa for a single transistor consisting of the cap layers, emitter layer, base layer and part of the collector layer; planarizing the mesa with insulation to isolate a single transistor; depositing a layer of photoresist at least over the mesa; delineating an emitter contact location; depositing a further layer of photoresist over the mesa; forming a photoresist mask out of the further photoresist, characterized by an emitter region pedestal including an emitter contact, surrounded by an emitter peripheral region and a base contact region, by etching the further photoresist through the cap layers to stop at the emitter layer; depositing a thin photo CVD layer of silicon nitride over the etched photoresist to cover the sidewalls of the pedestal, the sidewalls of the base contact region and the emitter peripheral region and base contact region; removing the silicon nitride from the top of the photoresist and the base contact region by using low pressure carbon tetrafluoride oxygen plasma anisotropic reactive ion etching to preserve the sidewall silicon nitride; selectively wet etching the base contact region to the base layer and depleting the emitter peripheral region aluminum gallium arsenide under the silicon nitride to passivate the emitter peripheral region; proton damaging the collector region beneath the base contact region; depositing base metal on the photoresist and in the base contact region; removing the photoresist and photoresist top of the pedestal along with the silicon nitride affixed thereto and the base metal not used for the base contact; and finishing a contact to the subcollector and a contact to the emitter in said emitter contact location.