Method and apparatus for reducing the effects of feedback switch charge injection into a plurality of serially connected sample data comparators

Claim 2

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, an apparatus for reducing effects of charge injection from the first and second feedback switches comprising: delay selection means for selecting an amount of signal delay; delay means, coupled to the delay selection means and to the second feedback switch, for delaying the receipt of the switching signal by the second feedback switch from the receipt of the switching signal by the first feedback switch by the selected amount of signal delay, the delay means comprising: voltage ramp means for ramping a voltage in response to the switching signal; comparing means, coupled to the voltage ramp means, for comparing the ramped voltage to a threshold value; and delayed signal generating means, coupled to the comparing means, for communicating the switching signal to the second feed back switch when the ramped voltage passes the threshold value.

Claim 3

The apparatus according to claim 1 wherein the delay selection means comprises ramp rate adjusting means, coupled to the voltage ramp means, for adjusting the rate of ramping of the voltage.

Claim 4

The apparatus according to claim 2 wherein the voltage ramp means comprises a capacitance.

Claim 5

The apparatus according to claim 3 wherein the voltage ramp means further comprises a current switch, coupled to the capacitance, for selectively allowing the communication of current with the capacitance in response to the switching signal.

Claim 6

The apparatus according to claim 4 wherein the ramp rate adjusting means comprises current limiting means, coupled to the current switch, for adjusting the rate of current flowing through the current switch.

Claim 7

The apparatus according to claim 5 wherein the current switch comprises a first transistor which flows current in response to the switching signal.

Claim 8

The apparatus according to claim 6 wherein the current limiting means comprises a second transistor coupled to the first transistor, the second transistor having a control terminal coupled for receiving a delay signal, the second transistor allowing an amount of current to flow through the first transistor corresponding to the magnitude of the delay signal.

Claim 9

The apparatus according to claim 7 further comprising an EE programmable current source coupled to the second transistor for providing the delay signal to the second transistor.

Claim 10

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, an apparatus for reducing effects of charge injection from the first and second feedback switches comprising: delay selection means for selecting an amount of signal delay; delay means, coupled to the delay selection means and to the second feedback switch, for delaying the receipt of the switching signal by the second feedback switch from the receipt of the switching signal by the first feedback switch by the selected amount of signal delay, the delay means comprising: first voltage ramp means for ramping a first voltage in a first direction in response to the switching signal; first comparing means, coupled to the first voltage ramp means, for comparing the ramped first voltage to a first threshold value; first delayed signal generating means, coupled to the first comparing means, for providing a first delayed switching signal when the ramped first voltage passes the first threshold value; second voltage ramp means for ramping a second voltage in a second direction opposite the first direction in response to the first delayed switching signal; second comparing means, coupled to the second voltage ramp means, for comparing the ramped second voltage to a second threshold value; and second delayed signal generating means, coupled to the second comparing means, for communicating the switching signal to the second feedback when the ramped second voltage passes the second threshold value.

Claim 11

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, an apparatus for reducing effects of charge injection from the first and second feedback switches comprising: delay selection means for selecting an amount of signal delay; delay means, coupled to the delay selection means and to the second feedback switch, for delaying the receipt of the switching signal by the second feedback switch from the receipt of the switching signal by the first feedback switch by the selected amount of signal delay, the delay means comprising: first voltage ramp means for ramping a first voltage in a first direction in response to the switching signal; first comparing means, coupled to the first voltage ramp means, for comparing the ramped first voltage to a first threshold value; first delayed signal generating means, coupled to the first comparing means, for providing a first delayed switching signal when the ramped first voltage passes the first threshold value; second voltage ramp means for ramping a second voltage in a second direction opposite the first direction in response to the first delayed switching signal; second comparing means, coupled to the second voltage ramp means, for comparing the ramped second voltage to a second threshold value; and second delayed signal generating means, coupled to the second comparing means, for communicating the switching signal to the second feedback when the ramped second voltage passes the second threshold value.

Claim 12

The apparatus according to claim 9 wherein the delay selection means comprises ramp rate adjusting means, coupled to the first voltage ramp means, for adjusting the rate of ramping of the first voltage.

Claim 13

The apparatus according to claim 9 wherein the delay selection means comprises ramp rate adjusting means, coupled to the second voltage ramp means, for adjusting the rate of ramping of the second voltage.

Claim 14

The apparatus according to claim 9 wherein the delay selection means comprises: first ramp rate adjusting means, coupled to the first voltage ramp means, for adjusting the rate of ramping of the first voltage; and second ramp rate adjusting means, coupled to the second voltage ramp means, for adjusting the rate of ramping of the second voltage.

Claim 15

The apparatus according to claim 12 wherein the first voltage ramp means comprises a first capacitance, and wherein the second voltage ramp means comprises a second capacitance.

Claim 16

The apparatus according to claim 13 wherein the first voltage ramp means further comprises a first current switch, coupled to the first capacitance, for selectively allowing the communication of current with the first capacitance in response to the switching signal, and wherein the second voltage ramp means further comprises a second current switch, coupled to the second capacitance, for selectively allowing the communication of current with the second capacitance in response to the first delayed switching signal.

Claim 17

The apparatus according to claim 14 wherein the first ramp rate adjusting means comprises first current limiting means, coupled to the first current switch, for adjusting the rate of current flowing through the first current switch, and wherein the second ramp rate adjusting means comprises second current limiting means, coupled to the second current switch, for adjusting the rate of current flowing through the second current switch.

Claim 18

The apparatus according to claim 15 wherein the first current switch comprises a first transistor which flows current in response to the switching signal, and wherein the second current switch comprises a second transistor which flows current in response to the first delayed switching signal.

Claim 19

The apparatus according to claim 16 wherein the first current limiting means comprises a third transistor coupled in series with the first transistor, the third transistor having a control terminal for allowing an amount of current to flow through the first transistor corresponding to the magnitude of a first delay signal applied thereto, and wherein the second current limiting means comprises a fourth transistor coupled in series with the second transistor, the fourth transistor having a control terminal for allowing an amount of current to flow through the second transistor corresponding to the magnitude of a second delay signal applied thereto.

Claim 20

The apparatus according to claim 17 wherein the magnitude of the first delay signal is the same as the magnitude of the second delay signal.

Claim 21

The apparatus according to claim 18 further comprising an EE programmable current source, coupled to the third and fourth transistors, for providing the first and second delay signals to the third and fourth transistors.

Claim 22

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, an method for reducing the effects of charge injection from the first and second feedback switches comprising the steps of: ramping a voltage in response to the switching signal; comparing the ramped voltage to a threshold value; and communicating the switching signal to the second feedback switch when the ramped voltage passes the threshold value.

Claim 23

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, an method for reducing the effects of charge injection from the first and second feedback switches comprising the steps of: ramping a voltage in response to the switching signal; comparing the ramped voltage to a threshold value; and communicating the switching signal to the second feedback switch when the ramped voltage passes the threshold value.

Claim 24

The method according to claim 20 further comprising the step of adjusting the rate of ramping of the voltage.

Claim 25

The method according to claim 21 wherein the voltage ramping step comprises the step of selectively allowing the communication of current with a capacitance through a current switch in response to the switching signal.

Claim 26

The method according to claim 22 wherein the ramp rate adjusting step comprises the step of adjusting the rate of current flowing through the current switch.

Claim 27

The method according to claim 23 wherein the current rate adjusting step comprises the step of allowing an amount of current to flow through the current switch corresponding to the magnitude of a delay signal.

Claim 28

The method according to claim 24 further comprising the step of providing the delay signal with an EE programmable current source.

Claim 29

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, a method for reducing the effects of charge injection from the first and second feedback switches comprising the steps of: ramping a first voltage in a first direction in response to the switching signal; comparing the ramped first voltage to a first threshold value; providing a first delayed switching signal when the ramped first voltage passes the first threshold value; ramping a second voltage in a second direction opposite the first direction in response to the first delayed switching signal; comparing the ramped second voltage to a second threshold value; and communicating the switching signal to the second feedback switch when the ramped second voltage passes the second threshold value.

Claim 30

In an apparatus having first and second serially coupled sample data comparators, the first sample data comparator including a first feedback switch coupled thereto that is activated by a switching signal, and the second sample data comparator including a second feedback switch coupled thereto that is activated by the switching signal, a method for reducing the effects of charge injection from the first and second feedback switches comprising the steps of: ramping a first voltage in a first direction in response to the switching signal; comparing the ramped first voltage to a first threshold value; providing a first delayed switching signal when the ramped first voltage passes the first threshold value; ramping a second voltage in a second direction opposite the first direction in response to the first delayed switching signal; comparing the ramped second voltage to a second threshold value; and communicating the switching signal to the second feedback switch when the ramped second voltage passes the second threshold value.

Claim 31

The method according to claim 26 further comprising the step of adjusting the rate of ramping of the first voltage.

Claim 32

The method according to claim 26 further comprising the step of adjusting the rate of ramping of the second voltage.

Claim 33

The method according to claim 26 further comprising the steps of: adjusting the rate of ramping of the first voltage; and adjusting the rate of ramping of the second voltage.

Claim 34

The method according to claim 29 wherein the first voltage ramping step comprises the step of selectively allowing the communication of current with a first capacitance through a first current switch in response to the switching signal, and wherein the second voltage ramping step comprises the step of selectively allowing the communication of current with a second capacitance through a second current switch in response to the first delayed switching signal.

Claim 35

The method according to claim 30 wherein the first ramp rate adjusting step comprises the step of adjusting the rate of current flowing through the first current switch, and wherein the second ramp rate adjusting step comprises the step of adjusting the rate of current flowing through the second current switch.

Claim 36

The method according to claim 31 wherein the first current rate adjusting step comprises the step of allowing an amount of current to flow through the first current switch corresponding to the magnitude of a first delay signal, and wherein the second current rate adjusting step comprises the step of allowing an amount of current to flow through the second current switch corresponding to the magnitude of a second delay signal.

Claim 37

The method according to claim 31 further comprising the step of providing the first and second delay signals with an EE programmable current source.

Claim 38

The method according to claim 31 wherein the magnitude of the first delay signal is the same as the magnitude of the second delay signal.