Patent US5179713A successfully refreshed from Google Patents.
US5179713A
Expired / Lapsed
US
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Apparatus for allowing external control of local bus read using zero wait stats input of combined I/O and DRAM controller
Assignee: Intel Corp
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Filing: 1990-06-06
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Granted: 1993-01-12
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Expires: 2010-06-06
Abstract
Abstract A single semiconductor chip containing both I/O bus controller and DRAM controller functions. A single pin on the chip is used to provide both a zero wait state input to the I/O bus controller and to provide a local bus access (LBA) signal for inhibiting both the I/O bus controller and the DRAM controller when an external device is doing an I/O or memory operation on the local bus. Logic isprovided to produce an inhibit signal to the I/O bus controller in response to the LBA signal. Another logic circuit is provided to inhibit the DRAM controller in response to the LBA signal only when there is a memory cycle signal from the microprocessor. The use of the single pin is possible since the zero wait state isgnal will only appear during the latter part of an I/O or memory cycle, which is mutually exclusive with the start of an I/O or memory cycle, which is the only time the LBA signal will appear.
Inventors
- 👤 Robert W. Catlin
- 👤 Robert M. Pleva
- 👤 Frank Spahn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:35
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1689; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
271 words
A semiconductor chip for providing support circuitry to facilitate the implementation of a computer system with a microprocessor, comprising: an I/O bus controller, having inputs for coupling to a local bus coupled to said microprocessor and outputs for coupling to a system bus not directly connected to said microprocessor, for providing I/O cycle timing signals to said outputs unless an inhibit signal is received on an inhibit input, and including a zero wait state input for receiving an external zero wait state signal indicating that said I/O cycle timing signals can be completed earlier; a DRAM controller, having inputs and outputs for coupling to said local bus, for providing memory cycle timing signals to said local bus; a zero wait state/local bus access input pin, coupled to said zero wait state input of said I/O bus controller, for providing a zero wait state/local bus access signal indicating the presence of either said external zero wait state signal or a local bus access signal from an external device doing an operation on said local bus; a memory/input-output pin for providing a memory/input-output signal from said microprocessor indicating a memory cycle in a first state and an I/O cycle in a second state; first logic means for inhibiting the provision of said I/O cycle timing signals by said I/O bus controller in response to the presence of said zero wait state/local bus access signal; and second logic means for inhibiting the provision of said memory cycle timing signals by said DRAM controller in response to the presence of said first state of said memory/input-output signal, and said zero wait state/local bus access signal.
Claim 2
Dependent Claim
271 words
A semiconductor chip for providing support circuitry to facilitate the implementation of a computer system with a microprocessor, comprising: an I/O bus controller, having inputs for coupling to a local bus coupled to said microprocessor and outputs for coupling to a system bus not directly connected to said microprocessor, for providing I/O cycle timing signals to said outputs unless an inhibit signal is received on an inhibit input, and including a zero wait state input for receiving an external zero wait state signal indicating that said I/O cycle timing signals can be completed earlier; a DRAM controller, having inputs and outputs for coupling to said local bus, for providing memory cycle timing signals to said local bus; a zero wait state/local bus access input pin, coupled to said zero wait state input of said I/O bus controller, for providing a zero wait state/local bus access signal indicating the presence of either said external zero wait state signal or a local bus access signal from an external device doing an operation on said local bus; a memory/input-output pin for providing a memory/input-output signal from said microprocessor indicating a memory cycle in a first state and an I/O cycle in a second state; first logic means for inhibiting the provision of said I/O cycle timing signals by said I/O bus controller in response to the presence of said zero wait state/local bus access signal; and second logic means for inhibiting the provision of said memory cycle timing signals by said DRAM controller in response to the presence of said first state of said memory/input-output signal, and said zero wait state/local bus access signal.
Claim 3
Dependent Claim
52 words
The semiconductor chip of claim 1 wherein said first logic means comprises an OR gate having a first input coupled to said zero wait state/local bus access input, a second input coupled to an output of said DRAM controller and an output coupled to an inhibit input of said I/O bus controller.
Claim 4
Dependent Claim
15 words
The semiconductor chip of claim 1 wherein said second logic means comprises an AND gate.
Claim 5
Dependent Claim
32 words
The semiconductor chip of claim 1 further comprising an open collector line coupled to said zero wait state/local bus access input pin and a pull-up resistor coupled to said open collector line.
Claim 6
Dependent Claim
345 words
A semiconductor chip for providing support circuitry to facilitate the implementation of a computer system with a microprocessor, comprising: an I/O bus controller, having inputs for coupling to a local bus coupled to said microprocessor and outputs for coupling to a system bus not directly connected to said microprocessor, for providing I/O cycle timing signals to said outputs unless an inhibit signal is received on an inhibit input, and including a zero wait state input for receiving an external zero wait state signal indicating that said I/O cycle timing signals can be completed earlier; a DRAM controller, having inputs and outputs for coupling to said local bus, for providing memory cycle timing signals to said local bus; a zero wait state/local bus access input pin, coupled to said zero wait state input of said I/O bus controller, for providing a zero wait state/local bus access signal indicating the presence of either said external zero wait state signal or a local bus access signal from an external device doing an operation on said local bus; a memory/input-output pin for providing a memory/input-output signal from said microprocessor indicating a memory cycle in a first state and an I/O cycle in a second state; an OR logic gate for inhibiting the provision of said I/O cycle timing signals by said I/O bus controller in response to the presence of said zero wait state/local bus access signal or the control of a cycle by said DRAM controller, said OR logic gate having a first input coupled to said zero wait state/local bus access input pin, a second input coupled to an output of said DRAM controller, and an output coupled to an inhibit input of said I/O bus controller; an AND gate having an output coupled to an inhibit input of said DRAM controller, a first input coupled to said memory/input-output pin, and a second input coupled to said zero wait state/local bus access pin; an open collector line coupled to said zero wait state/local bus access input pin; and a pull-up resistor coupled to said open collector line.
Claim 7
Dependent Claim
345 words
A semiconductor chip for providing support circuitry to facilitate the implementation of a computer system with a microprocessor, comprising: an I/O bus controller, having inputs for coupling to a local bus coupled to said microprocessor and outputs for coupling to a system bus not directly connected to said microprocessor, for providing I/O cycle timing signals to said outputs unless an inhibit signal is received on an inhibit input, and including a zero wait state input for receiving an external zero wait state signal indicating that said I/O cycle timing signals can be completed earlier; a DRAM controller, having inputs and outputs for coupling to said local bus, for providing memory cycle timing signals to said local bus; a zero wait state/local bus access input pin, coupled to said zero wait state input of said I/O bus controller, for providing a zero wait state/local bus access signal indicating the presence of either said external zero wait state signal or a local bus access signal from an external device doing an operation on said local bus; a memory/input-output pin for providing a memory/input-output signal from said microprocessor indicating a memory cycle in a first state and an I/O cycle in a second state; an OR logic gate for inhibiting the provision of said I/O cycle timing signals by said I/O bus controller in response to the presence of said zero wait state/local bus access signal or the control of a cycle by said DRAM controller, said OR logic gate having a first input coupled to said zero wait state/local bus access input pin, a second input coupled to an output of said DRAM controller, and an output coupled to an inhibit input of said I/O bus controller; an AND gate having an output coupled to an inhibit input of said DRAM controller, a first input coupled to said memory/input-output pin, and a second input coupled to said zero wait state/local bus access pin; an open collector line coupled to said zero wait state/local bus access input pin; and a pull-up resistor coupled to said open collector line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-12 | 1996-07-13 | 1997-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-12 | 2000-07-13 | 2001-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-12 | 2004-07-13 | 2005-01-12 | $7700.00 | Window Closed / Lapsed |